Temperature-dependent transition to progressive breakdown in thin silicon dioxide based gate dielectrics

The transition between well-defined soft and hard breakdown modes to progressive breakdown in ultrathin silicon dioxide based dielectrics is studied by means of the statistics of residual time (the time from first breakdown to device failure). By stressing metal-oxide-semiconductor test capacitors with an oxide thickness of 2.2nm under different gate bias and temperatures, it is demonstrated that low voltages and temperatures favor stable hard and soft breakdown modes, while high temperatures and voltages lead to a progressive breakdown controlled regime. Our results support the idea that no significant change of the involved physics occurs in the transition from one breakdown regime to the other. The continuous transition from one regime to the other permits one to clearly identify progressive breakdown as hard breakdown, which always requires a certain time to reach the device failure conditions.

The transition between well-defined soft and hard breakdown modes to progressive breakdown in ultrathin silicon dioxide based dielectrics is studied by means of the statistics of residual time ͑the time from first breakdown to device failure͒.By stressing metal-oxide-semiconductor test capacitors with an oxide thickness of 2.2 nm under different gate bias and temperatures, it is demonstrated that low voltages and temperatures favor stable hard and soft breakdown modes, while high temperatures and voltages lead to a progressive breakdown controlled regime.Our results support the idea that no significant change of the involved physics occurs in the transition from one breakdown regime to the other.The continuous transition from one regime to the other permits one to clearly identify progressive breakdown as hard breakdown, which always requires a certain time to reach the device failure conditions.© 2005 American Institute of Physics.͓DOI: 10.1063/1.1925316͔Gate oxide breakdown ͑BD͒ has been a reliability concern for many generations of metal-oxide-semiconductor technology.The issue is more serious than ever for the ultrathin oxides of present interest because the time to the first BD diminishes by many orders of magnitude ͑at constant gate voltage͒ when scaling the oxide thickness ͑T OX ͒ from 3 to 1 nm. 1 However, the BD does not always cause device failure, and this relaxes the reliability constraints. 2Dealing with the post-BD reliability is nevertheless difficult because the device failure criterion is application dependent and because the BD phenomenology apparently changes with T OX .In the 3 to 5 nm T OX range, two apparently stable BD modes have been identified as soft BD ͑SBD͒ and hard BD ͑HBD͒, 3 and a reliability model based on the HBD prevalence ratio ͑␣ HBD ͒ has been proposed. 46][7] The term "progressive breakdown" ͑PBD͒ has been coined to describe this type of BD, 6 and a related reliability methodology has been suggested. 5Other reliability models based on the failure by superposition of multiple successive BD events have also been proposed.These models also rely on the assumption of the existence of a stable SBD mode that does not cause the device failure. 8,9n this letter, we report the transition from the HBD/SBD regime to the PBD regime as a function of the stress conditions.We have stressed poly-Si/ SiO 2 /Si͑n͒ capacitors with T OX = 2.2 nm and oxide area of 10 −4 cm 2 at different gate voltages ͑V G ͒ and temperatures ͑T͒.The samples are stressed in accumulation under constant voltage conditions and the evolution of the current is monitored.The stress is periodically stopped to measure the stress-induced leakage current ͑SILC͒ at a lower voltage ͑V G = 1.5 V͒ close to the operation conditions of these devices in digital circuits.The measure of the time to the first BD ͑t BD ͒ of each sample is based on the detection of a current step in the SILC.However, the stress experiment is not stopped at the first BD and it continues until the failure of the device.Based on recent results about the impact of BD on the performance of basic circuits, 10,11 devices are considered to fail when the gate leakage reaches a threshold of 10 A at V SILC .The residual time ͑t RES ͒ is defined as the interval elapsed between first BD and device failure ͑t FAIL ͒, that is, t to those that suffer one or more SBD events prior to HBD.The intermediate plateau corresponds to F RES = ␣ HBD .Although the residual time associated to HBD is short, it is nonzero and it increases as V G is reduced.In other words, HBD is not instantaneous but progressive.This is consistent with the claim of Linder et al., who identified PBD with the HBD mode. 5In Fig. 2, the cumulative distribution of first BD ͑F BD ͒ and that of device failure ͑F FAIL ͒ are shown in the Weibull plot.It has been checked that all the devices fail due to the occurrence of a HBD event.The distributions F BD and F FAIL are roughly parallel in the Weibull plot, the vertical shift between them being ln͑␣ HBD ͒, as predicted by the HBD prevalence ratio model, 4 The values of ␣ HBD measured from the Weibull plot shift are perfectly consistent with those required to fit the residual time distributions of Fig. 1.In agreement with previous results, 4 increasing V G has the effect of increasing ␣ HBD , and this is why at V G = 4.5 V, almost all the devices show only HBD.In summary, the results obtained in 2.2 nm oxides stressed at T = −30 °C are perfectly compatible with the HBD prevalence ratio picture, which is based on the existence of two stable BD modes, SBD and HBD, as found in thicker oxides. 4Examination of the post-BD current-voltage I͑V͒ characteristics ͑not shown here͒ also supports this claim.It is also true, however, that at high voltages only HBD is measured and, since HBD is found to be progressive ͑a nonzero residual time is needed to reach the device failure condition͒, one can say that PBD is the dominant mode at high stress voltages.
The results obtained when samples are stressed at T = 140 °C are, however, qualitatively different.The range of V G has been changed to keep T BD and T FAIL within a reasonable test window because T accelerates the BD.The measured F RES is not bimodal in the considered V G range ͑see Fig. 3͒, and F BD and F FAIL are not parallel in the Weibull plot ͑Fig.4͒, but tend to diverge at low percentiles.These observations are compatible with F FAIL being dominated by the PBD mode.Our preliminary interpretation of these results is that temperature favors HBD events and, even if V G is reduced, no SBD events are observed at 140 °C.Hence, only PBD ͑i.e., progressive HBD͒ is the dominant mode under these stress conditions.However, to confirm this interpretation, we have stressed the devices at intermediate temperatures between −30 °C and 140 °C.Figure 5 shows the continuous transition from a bimodal residual time distribution at low temperatures to a single-mode distribution at higher  Temperature has also the effect of reducing the time required for HBD to reach the device failure condition.
In this letter, we have shown a continuous transition from HBD/SBD modes to the PBD mode ͑which is actually HBD͒ as a function of T ͑Fig.5͒ and V G ͑Fig. 1͒.Our results suggest that the observation of PBD mode in ultrathin oxides is not related to an essential change in the physics of the BD, but rather to the fact that SBD tends to disappear at the stress conditions required to keep T BD within reasonable limits.T OX certainly plays a relevant role because ␣ HBD changes from 1 to nearly 0 quite abruptly as a function of voltage, and this change takes place at a value of V G that depends on T OX . 12The thinner the oxide, the lower V G at which this transition occurs. 12Thus, for the same stress conditions, thinner oxides will appear as dominated by PBD, while the HBD/SBD picture seems adequate for thicker oxides.However, this does not mean that what is observed under stress conditions is representative of what happens under operating conditions.[7] One of the authors ͑J.S.͒ acknowledges the funding support of IBM Microelectronics, the Spanish Ministry of Science and Technology under contract number TIC2003-08213-C02 ͑partially funded by the FEDER program of the European Union͒, and the Departament d'Universitats, Recerca i Societat de la Informació de la Generalitat de Catalunya.

FIG. 3 .
FIG. 3. Distribution of residual time obtained by stressing the simples at 140 °C and three stress voltages.

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values of T. While at low T, both progressive HBD and SBD coexist in the measurement window, SBD almost disappears at high T.In other words, ␣ HBD increases with T and the plateau of the bimodal F RES moves up in the Weibull plot.