Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors

A physics-based model for the surface potential and drain current for monolayer transition metal dichalcogenide (TMD) field-effect transistor (FET) is presented. Taking into account the 2D density-of-states of the atomic layer thick TMD and its impact on the quantum capacitance, a model for the surface potential is presented. Next, considering a drift-diffusion mechanism for the carrier transport along the monolayer TMD, an explicit expression for the drain current has been derived. The model has been benchmarked with a measured prototype transistor. Based on the proposed model, the device design window targeting low-power applications is discussed.


Introduction
A great deal of interest in two-dimensional materials analogues of graphene has appeared among the scientific community since the demonstration of isolated 2D atomic plane crystals from bulk crystals [1]. Dimensionality is key for the definition of material properties and the same chemical compound can exhibit dramatically different properties depending on whether it is arranged in dots (0D), wires (1D), sheets (2D) or bulk (3D) crystal structure. Notably, experimental studies of 2D atomic crystals were lacking until recently because of the difficulty in their identification [1]. Representative of this class are the 2D monolayer of transition metal dichalcogenides (TMD) with a chemical formula MX 2 , where M stands for a transition metal and X for Se, S, or Te. The potential of this family of layered materials for flexible electronics was proposed by Podzorov et al., who demonstrate an ambipolar WSe 2 p-FET with high hole mobility (500 cm 2 /V-s) [2]. The electronic properties of TMDs vary from semiconducting (e.g., WSe 2 ) to superconducting (e.g., NbSe 2 ). The semiconducting monolayer TMDs, like MoS 2 , MoSe 2 , MoTe 2 , WS 2 , and WSe 2 are predicted to exhibit a direct gap in the range of 1-2 eV [3]. The wide gap together with a promising ability to scale to short gate lengths because of the optimum electrostatic control of the channel, by virtue of its thinness, make monolayer TMDs very promising for low power switching and optoelectronics applications. The first 2D crystal based FET was demonstrated using a monolayer MoS 2 as the active channel [4]. Low power switching with an I ON /I OFF 10 8 and subthreshold swing (SS) of 74 mV/decade at room temperature, was experimentally measured. More recently, a monolayer p-type WSe 2 FET with an optimum SS  60 mV/decade and I ON /I OFF >10 6 was demonstrated [5].
To boost the development of 2D-material based transistor technology, modeling of the electrical characteristics is essential to cover aspects as device design optimization, projection of performances, and exploration of low-power switching circuits. Some models aimed to explore the performance limits of monolayer TMD transistors have been reported assuming ballistic transport [6,7]. However, the behavior of state-of-the art devices is far from ballistic and a diffusive transport regime seems more appropriate. In this context, I propose a model for the current-voltage (I-V) characteristics of monolayer TMD FETs, based on the drift-diffusion theory. As a previous step a surface potential model, accounting for the 2D density-of-states (DOS 2D ) of monolayer TMDs, is proposed. The DOS 2D has a profound impact on the quantum capacitance, which is essentially different from that of a nanowire (1D) or a bulk (3D) material. Analytical expressions have been derived for both the surface potential and drain current covering both subthreshold and above threshold operation regions.

Surface potential model
Let us consider a dual-gate monolayer TMD FET with the cross-section depicted in the inset of Fig. 1a. It consists of one atomic layer thick TMD playing the role of the active channel. The source and drain electrodes contact the monolayer TMD and are assumed to be ohmic. The electrostatic modulation of the carrier concentration in the 2D sheet is achieved via a double-gate stack consisting of top and bottom gate dielectric and the corresponding metal gate. The source is grounded and considered the reference potential in the device. The electrostatics of this device can be understood using the equivalent capacitive circuit depicted in Fig. 2. Here, C t and C b are the top and bottom oxide capacitances and C q represents the quantum capacitance of the 2D sheet. The charge density (per unit area) is calculated by integrating the DOS 2D over all the energies and can be expressed as: (1) where Q p and Q n refer to the positive (holes) and negative (electrons) charge contributions, respectively; f(E) is the Fermi-Dirac function, and E F =qV c is the Fermi level.
The parameter V c represents the voltage drop across C q or surface potential. For the sake of getting a simple model f(E)1 for E<E F and f(E)exp((E F -E)/kT) has been assumed.
Noting that ∑ , with , where m* is the effective mass, E n represents the energy of the n th -subband, H(E) is the Heaviside function, and considering that the ground state (n=0) is the more relevant in determining the carrier density, then Eq.
(1) can be written as: ; , where E 0 =E g /2 and E g is the gap of the monolayer TMD. From Eq. (2), the quantum capacitance defined as C q =-dQ c /dV c , results in: where V gs -V gs0 and V bs -V bs0 are the top and back gate-source voltage overdrive, respectively. These quantities comprise work-function differences between the gates and the TMD monolayer, eventual charged interface states at the TMD monolayer/oxide interfaces, and intentional or unintentional doping of the TMD monolayer.

Drain current model
To model the drain current of a monolayer TMD p-FET a drift-diffusion transport is assumed under the form I ds =-WQ p (x)v(x), where W is the gate width, and v(x) the hole drift velocity v=E, where E is the electric field and  is the hole effective mobility. Applying E=-dV p (x)/dx, inserting the above expression for v, and integrating the resulting equation over the device length, the drain current becomes . In order to get an explicit expression for the drain current, the integral is solved using V c as the integration variable consistently expressing Q p as a function of V c :

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where V cs is obtained from Eq. (4) as V c (V p =0). Similarly, V cd is determined as V c (V p =V ds ).
Moreover, Eq. (4) provides the relation 1 , , where C q,p =-dQ p /dV c . Inserting this expression into Eq. (5), the following explicit drain current expression can be finally obtained: where g(V c ) takes different forms whether (above threshold region) or  6 is predicted by the model (Fig. 1a). Note that no interface trap capacitance (C it ) was needed to be included in the model to match the experiment because the near ideal subthreshold slope suggests that C it <<C ox . The output characteristics show saturation-like behavior at high V ds (Fig. 1b). Saturation velocity effects are not expected relevant for this transistor because ~2.5 / , giving L eff  L. At low V ds the model nicely reproduces the observed linear behavior, indicative of ohmic metal contacts. The agreement between the proposed model (solid lines) and the experiment (symbols) demonstrates its accuracy.
Next, by using the model, the tradeoff between I ON and I ON /I Off is calculated (Fig. 3). Ten In conclusion, a surface potential and drain current model for monolayer TMD transistors has been proposed, taking into account the 2D semiconducting nature of monolayer TMDs. The drain current is formulated assuming a drift-diffusion theory, which seems appropriate for explaining the experimental results of reported devices till date. These transistors hold promise for low-power switching applications. The proposed model should be valid for other transistors relying on 2D atomic layer thick channels.