The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to $10^5$. Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a"bias dependent barrier lowering effect"has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance.


I. INTRODUCTION
Graphene is one of the most studied materials because of its unique properties related to its two dimensional nature. It offers the possibility of integration with the existing semiconductor technology for next-generation electronic and sensing devices. In particular, its high conductivity makes it suitable for replacing traditional metal electrodes in Schottky diodes [1]- [5]. The graphene-semiconductor (GS) Schottky diode structure has been a platform to recent studies in interface transport mechanisms as well as for applications in photodetection, high-speed communications, solar cells, chemical and biological sensing, etc. [6]- [11]. However, despite the intensive researches into graphene electronics, graphene transistors exhibit a very poor ON-OFF current ratio (I on /I of f ), insufficient for digital applications, being the absence of an energy gap in graphene the reason behind. Few years ago, H. Yang et al. [12] proposed a three terminal device termed as "Barristor" to help overcoming this limitation, demonstrating an impressive 10 5 ON-OFF current ratio. In the barristor a top gate is added to the GS junction to control the Schottky barrier height (SBH) and so to achieve a large modulation of the diode current. In Yang's work an important aspect to suppress the formation of GS interface states and to avoid the appearance of Fermi-level pinning (FLP) was the optimized transfer process. In   There is an interface layer between G and S with thickness d. In order to be consistent with the sign of the charges in our model, in the figure Vox, ∆, Vg, ∆E F and φs are positives and V is negative. current rectification was observed by the modulation of the Fermi level of graphene with the gate voltage. The tunability of the Femi level was slightly weakened because of partial FLP produced by interface states in the GaSe. In this context, a thorough understanding of the physics and the potentialities of the gate controlled GS diode is of great importance and it must be subject of systematic investigation.
In this work, we extend the current understanding by proposing a physics based theoretical study of the electrostatics and I−V characteristics of the barristor taking into account the effects of possible interface trapped charges, resulting in FLP. We also explore the impact of scaling the device through the reduction of the gate oxide thickness.
II. MODEL Fig. 1a shows a sketch of the barristor studied in this paper. The bias voltage V ds produces a flow of carriers from source to drain forcing them to go from monolayer graphene to semiconductor, where a Schottky junction is formed. The SBH is modulated by a top gate voltage V g , which produces a fieldeffect through an insulator of thickness T ox . The equivalent circuit of the Barristor here considered is shown in Fig.  1b, where R represents the series resistance, including both contact (source and drain) and channel (graphene and silicon) resistances, V is the voltage drop across the Schottky juntion and I the current flowing across the barristor. In order to get a better understanding of the electrostatics, Fig. 1c shows the band diagram of the Metal/Oxide/Graphene/Semiconductor (MOGS) vertical structure, where a p-type semiconductor has been assumed over here, without loss of generality. Here W m , In our simulations we have assumed a neutral level qφ 0 = 0.4 eV, which is a typical value for silicon [17] . W g , and W s are the gate metal, graphene and semiconductor work functions, respectively. V ox and ∆ are the voltage drops across the gate oxide and the GS interface, respectively. ∆E F is the electrostatically induced shift of the graphene Fermi level respect to the Dirac point, qφ b is the value of the SBH, φ s is the surface potential of the semiconductor and qφ a is the difference between the Fermi level and the top of the valence band taken in the semiconductor's bulk. In our model we have assumed an interface layer of thickness d = 0.3 nm [14]. Aditionally, in order to take into account possible FLP because of surface states in the semiconductor, we have included a finite interface trapped charge Q ss in the model, assuming that those states are filled according to the graphene Fermi level [15]. The current characteristics of the device have been computed following a Landauer transport theory for the thermionic emission considering the finite density of states of graphene D = 2π −1 ( v f ) −2 |∆E F | = D 0 |∆E F | (v f is the Fermi velocity in graphene and the reduced Planck's constant) [5]: where is the effective area of the Schottky diode, q is the elementary charge, k B the Boltzmann constant, T the temperature, η is the ideality factor and τ is the time scale for carrier injection from the contact.
The SBH of the barristor is determined by solving Equations (2a)-(2d), which arise from the following conditions: (i) the total charge density in the heterojunction, including the gate contact metal charge Q m , the graphene layer charge Q g , the semiconductor charge Q s , and a possible interface trapped charge on the semiconductor Q ss must be conserved (Equation (2a)) and (ii) the sum of voltage drops around any loop from the band diagram (see Figure 1c) should be equal to zero (Equations (2b)-(2d)). Also the following relations are satisfied: [17]. The parameters s , N A and D it refer to the permittivity, doping concentration and interface trapped charge density of the semiconductor, respectively. The quantity in parentheses in Q ss is just the energy difference between the graphene Fermi level and the neutral level, so when they are the same, the net interface trapped charge is zero. In addition, the voltage drops across the oxide and interface layer are related with the charges as V ox = Q m /C ox and ∆ = −(Q s +Q ss )/C d , respectively. Here C ox = ox /T ox and C d = d /d describe the gate and interface layer capacitances per unit area. Finally, the series resistance R is related to the voltage drop across the Schottky juntion according to: By combining Eqs. 1-3 we can self-consistently solve both device's electrostatics and I-V characteristics (see Appendix A for an explanation). The main results revealing the impact of both FLP and scaling effects are shown in Figs. [2][3][4][5]. To validate our model we have benchmarked it with experimental results from two kind of barristors operating in opposite limits (see Appendix D): (i) a barristor based on a p-type silicon substrate and SiO 2 as gate insulator [12] operating in the Schottky limit (no FLP) and (ii) a barrisor based on a GaSe substrate and Al 2 O 3 as gate insulator [13] working in the Mott limit (strong FLP). We have assumed in our model the parameters reported in Table I, unless otherwise stated.

III. RESULTS AND DISCUSSION
Because the injection of the majority carriers (holes) from graphene to silicon is determined by φ b , the top gate modulates the magnitude of the current I. Fig. 2a shows, for two extreme cases, how the SBH can be modulated: i) without FLP, where D it = 0, and ii) with partial FLP, where D it has been assumed as 10 13 eV −1 cm −2 . It is worth noting that due to the coupling among Eqs. 2a-2d our model predicts, in general, that the SBH not only depends on V g but also on V ds , i.e. there is a "bias dependent barrier lowering effect", similarly  to the Drain Induced Barrier Lowering (DIBL) effect in short channel MOSFETs. In this sense, a barristor with p(n)-type semiconductor exhibits a reduction of its SBH when V ds negatively (positively) increases. From the inset of Fig. 2a we observe that there is a correlation between changes in the SBH and changes of the Fermi level shift, namely δφ b ≈ −γδ(∆E F ). In the Schottky limit (D it = 0), γ = 1 indicates that the Fermi level shift of graphene in absence of FLP is fully responsible for the variation of φ b . However, in a condition of partial FLP (D it ∼ 10 13 eV −1 cm −2 ) our simulations show γ = 0.6, which is a clear indication of a loss of sensitivity of the SBH with ∆E F and therefore with the gate voltage. An algebraic manipulation of Eq. 2c (assuming Q ss > Q s ), allows us to obtain the following analytical expression: where qφ b0 = W sg + qφ a + q 3 D it φ 0 /C d and W sg = W s − W g . From Eq. 4 we can see the role played by both D it and qφ 0 on the determination of SBH. The effects of the FLP on other electrical properties of the barristor will be shown below.
Next, we analyze the output characteristics of the barristor (Fig. 2b). As for the case of no FLP, a strong rectification could be induced provided V g >> 0V . In contrast, if FLP comes into play, the SBH becomes almost insensitive to the gate voltage (Fig. 2a) and rectification fades out. Unlike typical FET-like device operation, the diode current does not saturate as V ds increases, but increases almost linearly. However, near the diode turn-on regime (∼ 0-0.3V), I varies by several orders of magnitude as V g changes, resulting in a switching operation with a large I on /I of f ratio (see Appendix B). The inset of Fig. 2b shows the dependence of SBH on V ds for several gate voltages. In this case, two regions with different behavior can be observed: (i) at V ds 0 there is a nearly linear dependence and (ii) at V ds 0 the SBH saturates due to the effect of the series resistance. As T ox is reduced, the SBH becomes less sensitive to V ds (specially for negative gate voltages), but more sentitive to V g as shown in Appendix B. Fig. 2c shows the transfer characteristics of the barristor for both no FLP and partial FLP cases. In the former case, the curves for V ds > 0 exhibit the greatest on current, and among them, the corresponding to low values of V ds have the best ON-OFF current ratio. If the on(off) state is defined at the bias point V g = 0.1 V (V g = 3 V) with V ds = 0.1 V, the ON-OFF current ratio predicted by our model is in the range ∼ 10 − 10 8 for T ox between 100 and 2 nm (see Appendix B). This figure of merit, along with some key quantities such as I on , I of f as a function of D it are shown in Fig. 3 in order to evaluate the effect of the FLP. Again, the possible existence of FLP makes difficult an appropiate switching. Clearly I on is weakly dependent on D it for all values of T ox , while I of f has a strong dependence on it, especially for smaller values of T ox , resulting in larger values of I on /I of f . For instance, the device exhibits I on /I of f ∼ 10 4 for T ox ∼ 10 nm in the Schottky limit (D it = 0), but this high value can be even gotten assuming a partial FLP with D it ∼ 10 13 eV −1 cm −2 at smaller T ox of 2 nm.
Another interesting prediction of our model, displayed in Fig. 2c, is a shifting of the threshold gate voltage (V th ) induced by V ds , pretty the same as in short-channel MOSFETs due to the DIBL effect [18]. In Fig. 4a we show the dependence of V th on V ds at a constant threshold current I th = 10 −8 A. For comparison with the DIBL in conventional short-channel MOSFETs (tens of mV/V), the inset shows that ∆V th /∆V ds in the barristor is three orders of magnitude larger. The bias dependent barrier lowering effect reduces as T ox is further reduced because the gate plays a more dominant role. An explicit quadratic relation between V th and V ds has been found taking advantage of the insensitivity of the SBH to V ds when V ds 0 and T ox is small enough. Details of its derivation are given in Appendix C. That expression reads as: where a = q 2 D 0 /(2C ox ) and  Fig. 4b shows the effect of the interface trapped charge on the subthreshold voltage for several oxide thicknesses. It turns out that Vth becomes extremely sensitive to large values of D it (Mott limit). Next, we deal with the effect of the oxide thickness scaling on some figures of merit. Fig. 5a shows the ouput characteristics of a barristor having T ox = 10 nm and D it = 0, which can be compared with the case T ox = 100 nm shown in Fig. 2b. In the inset, we have plotted the SBH as a function of V g . From it, clearly the V ds control over the SBH decreases when T ox is smaller. That is due to the strong gate control resulting in a distribution of charge, mostly, between gate metal electrode and graphene, therefore the charge in the semiconductor is small and the drain can hardly modulate it.
In Fig. 5b we show the average subthreshold slope at V ds = 0.1 V as a function of T ox with and without FLP. The presence of FLP degrades the subthreshold swing (SS), being this effect more important at large T ox and low permitivities. For instance, using a high-k as gate insulator (HfO 2 ) in combination with small T ox results in SS much closer to 60 mV/dec. Finally, Fig. 5c shows the value of V g,of f , as a function of T ox , needed to keep a constant value I on /I of f = 5 × 10 4 , again at V g,on = 0.1 V, and V ds = 0.1 V. For instance, selecting V g,of f between 2V -3V an ON-OFF current ratio of ∼ 10 4 is feasible for T ox 10 nm, in the situation of no FLP.

IV. CONCLUSIONS
In conclusion, we have theoretically studied the electrostatics and current-voltage characteristics of the barristor device considering effects of FLP arising by possible presence of surface states, similarly to the metalsemiconductor junction. Our study suggests that the barristor is a feasible graphene logic device achieving high enough ON/OFF current ratio. When FLP dominates the barristor's electrostatics, then the gate electrode cannot modulate the SBH any more and rectification could be totally lost. On the other hand, our model has revealed that the barristor exhibits changes of the threshold voltage induced by the drain-source voltage, similarly to the Drain Induced Barrier Lowering in short channel MOSFETs. It turns out that the barristor has to be biased at low V ds to get a sufficient ON-OFF current ratio.
As a final note, here we have investigated the impact that a non-ideal interface might have in the barristor operation, and we have pointed out the role of oxide thickness scaling could have to get appropiate digital performance.

APPENDIX A SOLUTION OF THE EQUATIONS.
The non-linear system of equations 1-3, which involve both the electrostatics and the current of the device, can be understood as a system of three coupled equations where the ouput variables are ∆E F , φ s and V and the input parameters are V ds , V g , and the geometrical and electrical parameters listed the Table I. Considering that V ox = V ox (∆E F ) from Eq. 2b, φ b = φ b (φ s , V ) from Eq. 2d and the definitions of the charges, we can express Eq. 2a as follows: By using the definition of the voltage drop ∆ = − (Q s + Q ss ) /C d across the interface layer, Eq. 2c reads as: (8) Also, Eqs. 1 and 3 can be combined to get: (9) In summary, Eqs. 7-9 can be rewritten and solved as a set of three non-linear coupled equations with ouput variables ∆E F , φ s and V , namely: (10c)

APPENDIX B ADDITIONAL SIMULATIONS FOR THE BARRISTOR
In this section we show additional simulations in order to get a better understanding of the barristor's properties without FLP for several oxide thickness. We have considered both R = 0 and R = 250 kΩ cases in figures 6-7 and figures 8-10, respectively. The rest of parameters are from Table I.

APPENDIX C BARRISTOR'S THRESHOLD VOLTAGE AND ITS DEPENDENCE
ON THE DRAIN VOLTAGE (NO FLP) In order to obtain the barristor's threshold voltage V th as a function of the drain-source voltage V ds , we start from the equation (1) of the main text, which can be rewritten as: To determine V th , let us assume the barristor biased in the off state (with V g > 0) and V ds ≥ 0.1 V. Under these conditions, we can safely assume V ds − IR >> 3ηv t and φ b >> 3v t . Let us define now V th as the gate voltage needed to deliver a current I th = 10 −8 A. So, Eq. 11 can be approximated as: After some algebra we get Then we use a first order Taylor series expansion of the logarithm function, so we can write log(u) ≈ log(u 0 )+u/u 0 − 1 for u around u 0 , being u 0 >> 1. Using that result, we can find an expression for the SBH as an explicit function of V ds : where we have assumed u 0 = φ/v t is within the range 20-100 (See Figs. 6 and 9). The expression of Eq. 14 holds for any T ox . If we further assume T ox 10 nm, then the gate totally controls the electrostatics and the charge is distributed between the metal gate and the graphene, i. e. Q s ∼ 0 and Q m + Q g ≈ 0. Then, by combining Eqs. 2a-2b from the main text, we obtain: The solution of Eq. 15 can be expressed as: where a = q 2 /(C ox π 2 v 2 f ) = q 2 D 0 /(2C ox ) and ω = W g − W m + qV g . Now, by combining Eqs. 2c-2d, an expression of the SBH as a function of the threshold voltage can be obtained: where ω th = W g − W m + qV th . Finally, by replacing Eq. 14 into Eq. 17 and after some manipulation, an explicit relation V th = V th (V ds ), valid for small T ox , is obtained: where η * = η(1 − 1/u 0 ) and In this Section we benchmark our model with two experiments reported in the literature, namely: a graphene-Si barristor working in the Schottky limit [12], and a graphene-Gase barristor working in the Mott limit [13]. Fig. 11. Logarithmic I-V characteristic of a Graphene-Si barristor at Vg = 0. Symbols: Experimental measurements from Ref. [12] and solid line: results from our model in this work. To capture the trends given by the experimental data the device has been assumed to operate close to the Schottky limit, with D it = 0, qφ 0 = 0.4 eV, η = 1.1, A = 30 × 10 −5 cm 2 and R = 100 Ω.  [13] and (b) results from our model in this work. To capture the trends given by the experimental data the device has been assumed to operate close to the Mott limit, with D it = 2 × 10 14 eV −1 cm −2 . Other assumed parameters are: qφ 0 = 1 eV, η = 1.025 and R goes between 0.3 − 3 GΩ.