This is the accepted version of the article: Miranda, Enrique Alberto; Morell Pérez, Antoni; Muñoz Gorriz, Jordi; [et al.]. «Simple method for monitoring the switching activity in memristive cross-point arrays with line resistance effects». Microelectronics Reliability, Vol. 100-101 (September 2019), art. 113327. DOI 10.1016/j.microrel.2019.06.019 This version is avaible at https://ddd.uab.cat/record/215345 under the terms of the license Simple method for monitoring the switching activity in memristive cross-point arrays with line resistance effects 1 line space a,* b a a E. Miranda , A. Morell , J. Muñoz-Gorriz , J. Suñé 1 line space a Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193 Cerdanyola del Valles, Spain b Departament de Telecomunicació i Enginyeria de Sistemas, Universitat Autònoma de Barcelona, 08193 Cerdanyola del Valles, Spain 2 lines space Abstract A simple method for monitoring the switching activity (forming, set, reset events and stuck-at-0/1 faults) in memristive cross-point arrays with line resistance effects is proposed. The method consists in correlating incremental current changes in a four-terminal configuration with the location of the switching cell within the array. To this end the potential drop in the interconnection wires as well as the nonlinearity of the switching elements are considered. The problem is solved by iterating the Kirchhoff’s current law for the coupled word and bit lines with appropriate boundary conditions. The main experimental advantage of the proposed method is that only four SMUs (source-measurement unit) are needed to identify the switching cell. In this way, our method could greatly contribute to foster the system-level reliability analysis of cross-point arrays since additional circuitry for the individual addressing of the switching device is not required. 1 line space 1. Introduction CPAs from a system-level approach. The idea is to rework the 2D current-ratio (CR) technique used to Memristive cross-point arrays (CPA) are nowadays localize the occurrence of successive breakdown intensively investigated by academia and industry events in MOS transistors for the CPA case [11]. The because of their relevance in the fields of method consists in biasing the structure appropriately information storage and artificial intelligence [1]. and correlating incremental current changes in the CPAs are often associated with the matrix-vector terminals with the location of the switching event. multiplication operation which is a key operation in This requires determining the voltage distribution at many computationally intensive algorithms [2,3]. In each node of the CPA considering the memory devices, the direct interconnection of interconnection resistances. Recall that this voltage devices (selectorless CPA) leads to the so-called distribution modifies as the switching cells change sneak-path problem [4]. A CPA basically consists in their states. This is a complex nonlinear problem that the combination of two networks of vertical (N bit is often solved using circuit simulators [12]. As the lines) and horizontal (M word lines) wires with a switching device, we will use in this work the passive nonvolatile memory device or memristor at memdiode (diode with memory) which allows to each intersection (see Fig. 1). Both for memory and simulate a continuum of states by simply changing a neuromorphic applications, the conductance of each parameter in the model [13]. memristive device is set to a specific value representing a memory state or a synaptic weight, respectively. In addition, as the fabrication technology improves and the device dimensions shrink, the line resistance in CPAs is becoming a serious issue [5,6]. CPAs are not exempt from suffering faults related to the switching capability both associated with the fabrication process and with the lifetime of the devices [7-10]. This work explores Figure 1. a) Typical MxN CPA with line resistance. b) Detail of the intersection between word and bit lines. The symbol the possibility of investigating reliability aspects of corresponds to the memdiode. __________________________________________ * Corresponding author. enrique.miranda@uab.cat 2. Method description and equations The boundary conditions at the four terminals in Fig. 2a will depend on the kind of test we want to The method proposed to identify the locations carry out. We can leave the terminals opened or (1iM,1jN) of the switching cells is based on closed. For instance, in a constant voltage stress detecting current changes in a four-terminal experiment, we bias the top and bottom wire configuration. The CPA is connected as depicted in networks with voltages VW=VE=1V and VN=VS=0V. Fig. 2a. VN, VS, VE, VW and IN, IS, IE, IW correspond to Of course, these values will depend on the particular the North, South, East and West voltage and current characteristics of the array but should be in a range terminals, respectively. The arrows indicate the compatible with the switching process of interest positive convention for the currents. Figure 2b (forming, set, reset, stuck-at faults, etc.). Figure 3 illustrates the connections at a particular intersection. shows the voltage distribution Vij-V’ij in a 16x16 Notice that the switching element between word and CPA when all the devices are in the high resistance bit lines is represented by a memdiode. state (HRS). Notice the surface curvature associated with the voltage drops caused by the wire a) b) resistances. It is clear that not all the devices see the same voltage drop. For example, this could strongly affect the set time of the devices which is expressed as [14]: 𝜏 𝜏 𝑒𝑥𝑝 (3) where 0 and V0 are constants. As observed in Fig. 3, the largest voltage drops occur at the corners of the Figure 2. a) Four-terminal connection considered in this work and current convention. b) Detail of the intersection between the top array, and therefore those devices are expected to and bottom wire networks. switch first. If we want to correct this nonuniform voltage distribution, resistance compensations at the It is easy to demonstrate that, according to terminal wires are an option [15]. Importantly, in Kirchhoff’s current law, Vij and V’ij, the voltages at what follows, the temporal aspect of the switchings the top and bottom networks, respectively, can be is not considered. From here on the attention is expressed as: exclusively focused on determining the position of the switching event within the array. 𝑉 𝑉 𝑉 𝑟𝐼 (1) Similarly to the 2D CR method used to localize the failure sites in the gate oxide of a MOS transistor 𝑉 𝑉 𝑉 𝑟𝐼 (2) [11], we can locate the switching device using: ∆ where 𝐼 𝐼 𝑉 𝑉 is the current that flows 𝑖 𝑖𝑛𝑡 1 (4) ∆ ∆ through the memdiode ij and r he resistance of each ∆ section of the wire. Notice that (1) and (2) define a 𝑗 𝑖𝑛𝑡 1 (5) ∆ ∆ system of coupled nonlinear equations that can be solved by iteration. where IN, IW, IS, and IE refer to the incremental a) b) 1.05 0 current changes at the four terminals. int is the Wire resistance [] 1.00 5 10 20 integer part of the number. The basic idea is that 0.95 40 each switching event generates a perturbation in the 0.90 CPA voltage/resistance distribution which is Voltage [V] 0.85 detected in the terminal currents. The magnitude of 0.80 the current changes is related to the distance of the 0.75 switching cell to each of the opposite terminals. 0.70 0.65 0.60 0 2 4 6 8 10 12 14 16 3. Memdiode model Position Figure 3. a) Voltage distribution at the CPA nodes (VW=VE=1V and VN=VS=0V). b) Voltage distribution as a function of the In this work, the switching elements at the position along the 16x16 network and wire resistance r. intersections of the lines are modelled as memdiodes. A memdiode is a behavioral memory device a) Vij V’ij Vij ‐ V’ij represented by a diode with hysteretic properties [13,16]. For the sake of completeness, it is succinctly reviewed here. Physically, the memdiode expresses the presence of a potential barrier (Schottky, tunneling, quantum constriction, etc.) that controls the electron flow. This barrier remains stable (even if the power is turn off) until it is modified by a set or reset process. The memdiode model follows a typical memristive scheme, i.e. its conduction properties are described by two equations, one equation for the electron transport (I-V) and a second equation for the memory state of the device (-V) which changes according to the input signal. Since we will not deal here with hysteretic properties and switching transients, a discussion about the memory operator is irrelevant for the present analysis. The equation for the I-V characteristic of a memdiode is expressed as: 𝐼 𝑉 𝑠𝑔𝑛 𝑉  𝛼𝑅 𝑊 𝛼𝑅𝐼  𝑒𝑥𝑝 𝛼 |𝑉| 𝑅𝐼  𝐼  (6) where 𝐼  𝐼 1 𝜆 𝐼 𝜆 is the diode current amplitude,  a positive constant related to the particular features of the conduction mechanism, R a series resistance, and W the Lambert function. (1) is the solution of two antiparallel diodes with a single series resistance. The inverse currents of the diodes are neglected. Imin and Imax are the minimum and maximum values of the current amplitude, respectively. V is the absolute value of the applied bias and sgn the sign function. As shown in Fig. 4, as 𝐼 increases in (6), the I-V curve changes its shape from linear-exponential to linear, as experimentally observed in many memristive devices.  is a control parameter that runs between 0 (HRS) and 1 (LRS). The model allows testing intermediate conduction states as well. Here, we will focus on the extreme situations =0 and =1. Notice that, in our approach, there is no need to consider separate expressions for the HRS and LRS I-V curves as in previous works 3 2 b) [17,18]. Expression (6) is used in (1) and (2). IW Current [mA] 1 IE 0 IN -3 10 I0max=1E-3A -1 IS I0min=1E-7A  -2 -4 -1 10 alpha=2eV R=1k -3 -5 10 16 c) (10,15) Current [A] 14 (7,12) (16,6) -6 12 10 10 Location 8 -7 0 (1,9) (14,12) 10 1E-4 6 (1,1) 4 j 1E-3 -8  1E-2 2 (13,4) i 10 1E-1 0 0 1 2 3 4 5 6 7 8 1 -9 10 Event # 0.1 1 Voltage [V] Figure 5. Switching events in a 16x16 CPA. a) Voltage distribution in the top/bottom layers and difference. b) Evolution Figure 4. I-V curves for a memdiode. The parameter  changes the of the terminal currents. c) Location of successive events. Follow current magnitude from HRS (=0) to LRS (=1) in a continuous the arrows in a). r=5, VW=VE=1V and VN=VS=0V. way. 3. Results and discussion Figure 6 illustrates the case in which all memristors in the 16x16 CPA are initially in LRS. As the cells Once the location procedure for the switching switch off (see Fig. 6a), the terminal currents cell and the conduction model for the memristive decrease. Again, this information is used to detect structure are established, eqns. (1) and (2) can be the location of the successive switching events. solved numerically. Let’s consider first a 16x16 It is worth emphasizing that since the method is CPA. Figure 5a shows the hypothetical evolution of based on the incremental modification of the the array caused by the application of constant currents, the initial state configuration can be as voltages (VW=VE=1V and VN=VS=0V) to the complex as required. In this regard, Fig. 7 shows the terminals. The top row in Fig. 5a corresponds to all case of a 32x32 CPA with a random distribution of devices in HRS. The second row shows a first LRS and HRS cells. The method is able to detect that OFF/ON switching event. The intersection of the the memdiode (i=20,j=20) switched off. For larger horizontal and vertical lines clearly points out the arrays the ability of the method to detect a switching location of the switching cell. Figure 5b shows the event strongly depends on the current window evolution of the four terminal currents. The (difference between LRS and HRS) and on the incremental data are used to compute the locations computation errors involved. Of course, in practice (see Fig. 5c) of the events via eqns. (4) and (5). the method will be ultimately limited by the 80 resolution of the experimental setup, the noise in the 79 78 IW a) system, the variability of the switching process, etc. Current [mA] 77 76 IE IN These issues require an in-depth analysis. -77 IS -78 -79 -80 18 16 4. Conclusions 14 b) 12 A simple method for determining the location of Location 10 j 8 i 6 4 a switching cell within a cross-point array was presented. The method is based on monitoring the 2 0 0 1 2 3 4 5 6 7 8 Event # evolution of the currents in a four terminal Figure 6. a) Evolution of the terminal currents. b) Location of configuration. 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