www.nature.com/npj2dmaterials ARTICLE OPEN Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances Francisco Pasadas 1*, Enrique G. Marin 2,3 , Alejandro Toral-Lopez 2,4 , Francisco G. Ruiz 2 , Andrés Godoy 2,4 , Saungeun Park5, Deji Akinwande5 and David Jiménez 1 We present a physics-based circuit-compatible model for double-gated two-dimensional semiconductor-based field-effect transistors, which provides explicit expressions for the drain current, terminal charges, and intrinsic capacitances. The drain current model is based on the drift-diffusion mechanism for the carrier transport and considers Fermi–Dirac statistics coupled with an appropriate field-effect approach. The terminal charge and intrinsic capacitance models are calculated adopting a Ward–Dutton linear charge partition scheme that guarantees charge conservation. It has been implemented in Verilog-A to make it compatible with standard circuit simulators. In order to benchmark the proposed modeling framework we also present experimental DC and high-frequency measurements of a purposely fabricated monolayer MoS2-FET showing excellent agreement between the model and the experiment and thus demonstrating the capabilities of the combined approach to predict the performance of 2DFETs. npj 2D Materials and Applications (2019)3:47 ; https://doi.org/10.1038/s41699-019-0130-6 1234567890():,; INTRODUCTION potential and drift-diffusion approaches but the dynamic behavior Since the emergence of graphene, over a surprisingly short period of the TMD-FETs was not treated.5 Also based on surface potential of time, an entire new family of two-dimensional materials (2DMs) and drift-diffusion arguments, Parrish et al.6 presented a compact has been discovered.1 Some of them are already used as channel model for graphene-based FETs for linear and non-linear circuits, materials in FETs, being promising candidates to augment silicon but the dynamic regime description was roughly estimated by and III–V compound semiconductors via heterogeneous integra- equally splitting the total gate capacitance between gate-drain tion for advanced applications. In this context, the development of and gate-source capacitances. A charge-based compact model for electrical models for 2D semiconductor-based FETs (2DFETs) is TMD-based FETs only valid for the static regime but simulta- essential to: (1) interpret experimental results; (2) evaluate their neously including interface traps, ambipolar current behavior, and expected digital/RF performance; (3) benchmark against existing negative capacitance was proposed by Yadav et al.7 Taur et al.8 technologies; and (4) eventually provide guidance for circuit presented an analytic drain current model for short-channel design and circuit-level simulations. 2DFETs combining a subthreshold current model based on the Several compact models for three-terminal FETs based on solution to 2D Poisson’s equation and a drift-diffusion approach to graphene and related 2D materials (GRMs) have been recently get an all-region static description. Rahman et al.9 discussed a published encompassing both static and dynamic regimes.2–10 In physics-based compact drain current model for monolayer TMD- particular, Suryavanshi et al.2 proposed a semi-classical transport FETs considering drift-diffusion transport description and the approach for the drain current combining the intrinsic FET gradual channel approximation to analytically solve the Poisson’s behavior with models of the contact resistance, traps and equation. Unfortunately, none of them faced the dynamic regime impurities, quantum capacitance, fringing fields, high-field velocity operation. Finally, Gholipour et al.10 proposed a compact model saturation and self-heating. However, the dynamic regime is that combines both the drift-diffusion and the Landauer–Buttiker described using a charge model derived for bulk MOSFETs11 that approaches to properly describe the long- and short-channel FETs fails to capture the specific physics of the 2D channel, since it in flexible electronics, respectively. As a key feature, the considers that the channel is always in a weak-inversion regime mechanical bending is considered by linearly decreasing the and therefore the channel charge can be assumed to be linearly channel material bandgap with respect to the applied strain. distributed along the device. Wang et al.3 reported on a compact However, the capacitance model was roughly approximated by model restricted to the static regime of graphene FETs and based considering that the top (back) gate-drain and top (back) gate- on the “virtual-source” approach, valid for both the saturation and source capacitances are just the geometrical top (back) gate linear regions of device operation. Also based on the “virtual- capacitance. In summary, up to date the dynamic description of source” approach, Rakheja et al.4 studied quasi-ballistic graphene 2DFETs has been either roughly approximated or not specifically FETs. Nevertheless, they also employed the approximation derived addressed for such devices. Our aim is to develop an accurate and for bulk MOSFETs11 for the dynamic regime description even physics-based compact model of the terminal charges and though the channel material considered is graphene. Jiménez corresponding intrinsic capacitances of four-terminal (4T) 2DFETs early developed a model describing the drain current for single valid for all operation regimes. In doing so, we present such a layer transition metal dichalcogenide (TMD) FETs based on surface model together with the drain current equation, developed by 1 Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193 Bellaterra (Cerdanyola del Vallès), Spain. 2Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain. 3Dipartimento de Ingegneria dell’Informazione, Università di Pisa, 56122 Pisa, Italy. 4Excellence Research Unit “Modeling Nature” (MNat), Universidad de Granada, 18071 Granada, Spain. 5Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78758, USA. *email: francisco.pasadas@uab.es Published in partnership with FCT NOVA with the support of E-MRS F. Pasadas et al. 2 some of us,12 based on drift-diffusion theory where the surface mandatory to include them in order to achieve an accurate potential is the key magnitude of the model. So that, the predictive TCAD tool. For n-type devices, acceptor-like traps combination of both approaches gives rise to a compact large- (which are negatively charged when occupied by electrons and signal model suitable for commercial TCAD tools employed in the are energetically located in the upper half of the bandgap15) simulation of circuits based on 2DFETs. The model has been contribute the most to the device electrical characteristics.16 shown to reproduce with good agreement DC and high-frequency Assuming the traps are situated at an effective energy Eit = – qVit measurements of a fabricated n-type MoS2-based FET, and has below the conduction band, the occupied trap density can be written been used to predict the output transient of a three-stage ring as nit = Nit/(1 + exp(Vc − Vit/Vth)), where Nit is the effective trap oscillator. density considered to be a delta function in energy. The trap charge density is then Qit = –qnit and the interface trap capacitance Cit at the oxide–semiconductor interface (taken as a RESULTS combination from both interfaces of the ultra-thin 2D channel) Large-signal model of four-terminal 2DFETs can be computed as: We first deal with the development of the large-signal model of 4T dQit qNit 1 2DFETs by the sequential formulation of the electrostatics, the Cit ¼ ¼  ; (2) dVc 2Vth 1 þ cosh Vc  Vit drain current equation, the terminal charge model, and the Vth corresponding intrinsic capacitance description. The cross-section of the considered dual-gated 2DFET is where Vth = kBT/q is the thermal voltage, kB is the Boltzmann depicted in Fig. 1a. For the sake of brevity, we derive here the constant, and T is the temperature. The term Cit adds to the expressions for an n-type device (the extension to a p-type quantum capacitance Cq, as shown in Fig. 1c. transistor can be obtained straightforwardly). Provided that the We can, thus, find an expression to calculate the overall net semiconductor bandgap is not too small, we can assume that mobile sheet density assuming a parabolic dispersion relationship p(x) ≪ n(x) in all regimes of operation, where p(x) and n(x) are the modeled in the effective mass approximation and using hole and electron carrier densities, respectively. Upon application Fermi–Dirac statistics12:   of 1D Gauss’ law to the double-gate stack shown in Fig. 1b, the  Vc 1234567890():,; Qnet ðxÞ ¼ qnðxÞ ¼ Cdq Vth uðVc Þ; uðVc Þ ¼ ln 1 þ e Vth ; (3) electrostatics can be described using the equivalent circuit depicted in Fig. 1c: where Cdq = q2D0 is defined as the degenerated-quantum   capacitance, which corresponds to the upper-limit achievable Qnet ðxÞ þ Qit ðxÞ ¼ Ct Vg  Vg0  VðxÞ þ Vc ðxÞ  Cb ðVb  Vb0  VðxÞ þ Vc ðxÞÞ; when the 2D carrier density becomes heavily degenerated.17 (1) D0 = gK(mK/2πħ2) + gQ(mQ/2πħ2)exp[−ΔE2/kBT] is the 2D density of where Qnet(x) = q(p(x) – n(x)) is the overall net mobile sheet charge states, with ħ being the reduced Planck’s constant, gK (gQ) the density and q is the elementary charge. Ct = ε0εt/tt (Cb = ε0εb/tb) is degeneracy factor and mK (mQ) the conduction band effective the top (back) oxide capacitance per unit area where εt (εb) and tt mass at the K (Q) band valley. In most TMDs, the second (tb) are the top (back) gate oxide relative permittivity and conduction valley, labeled as Q valley, is non-negligible since the thickness, respectively; and Vg – Vg0 (Vb – Vb0) is the overdrive energy separation between the K and Q conduction valleys, ΔE2, is top (back) gate voltage. These latter quantities comprise work- only around 2kBT.18,19 Thus, two conduction band valleys may function differences between the gates and the 2D channel and participate in the transport process. The rest of valleys are, on the any possible additional charges due to impurities or doping. The contrary, far away in energy to contribute to the electrical energy qVc(x) = EC(x) − EF(x) represents the shift of the quasi-Fermi conduction,20 and hence can be neglected for practical purposes. level with respect to the conduction band edge and –qV(x) = EF(x) The quantum capacitance of the 2DM can be computed by is the quasi-Fermi level along the channel. This latter quantity evaluating Cq = dQnet/dVc resulting in: must fulfill the boundary conditions: (1) V(x = 0) = Vs (source Cq ¼ Cdq ð1  eu Þ: (4) voltage) at the source end; (2) V(x = L) = Vd (drain voltage) at the drain end. Due to the complexity of Eq. (1) and considering the relation 2D crystals are far from perfect and suffer from diverse non- between Qnet and Vc given by Eq. (3), it is not possible to get an idealities. In particular, interface traps are unavoidable in FETs, explicit expression for Vc as a function of the applied bias. even for those processed by state-of-the-art CMOS technology,13 However, an iterative Verilog-A algorithm can be implemented to impacting negatively the performance of 2DFETs.14 Therefore, it is evaluate the chemical potential at the source and drain edges, Fig. 1 a Cross-section of the 2DFET considered in the modeling framework. A 2DM plays the role of the active channel. b Scheme of the 2DM- based capacitor showing the relevant physical and electrical parameters. c Equivalent capacitive circuit of the 2DFET. npj 2D Materials and Applications (2019) 47 Published in partnership with FCT NOVA with the support of E-MRS F. Pasadas et al. 3 which are the relevant quantities determining the drain current. In (9) and (11) to get the terminal charges Qg, Qb, and Qs, doing so, Vcs = Vc|V=Vs and Vcd = Vc|V=Vd are obtained, respectively, respectively. Qd in Eq. (13) has been simplified by assuming that from Eqs. (1) and (3) by a construct21,22 which lets the circuit the term e(2ud+2us) is prevalent over other low-order terms, e.g., eud simulator to iteratively solve both equations during run-time. and eus. In the diffusive regime, the drain current of a 2DFET can be Once the terminal charges are evaluated, a four-terminal FET accurately computed by the following compact expression12: can be modeled with 4 self-capacitances and 12 intrinsic   2  transcapacitances given by: W Cdq us  u2d Ids ¼ μ Cdq Vth 2 1þ þ ðeud  eus Þ ; (5) ∂Qi ∂Qi L Ctb 2 Cij ¼  i≠j Cij ¼ i¼j i; j ¼ g; d; s; b; where us = u(Vcs) and ud = u(Vcd); Ctb = Ct + Cb; W and L are the ∂Vj ∂Vj device width and length, respectively; and µ is the carrier mobility (14) which has been assumed to be dependent of the applied electric where Cij describes the dependence of the charge at terminal i field, carrier density, and temperature as in ref. 2 Once we have a with respect to a varying voltage applied to terminal j assuming suitable expression for describing the static behavior of the that the voltage at any other terminal remains constant. Due to device, the dynamic response must be analyzed to build a large- charge conservation and considering a reference-independent signal model. In doing so, the terminal currents in the time model, only nine independent capacitances are needed to domain can be computed as: describe the 4T device. In addition, taking advantage of the dQk dvg dvd dvs dvb relations between the top- and back-gate capacitances,25 the ik ðtÞ ¼ ¼ Ckg þ Ckd þ Cks þ Ckb ; (6) dt dt dt dt dt computation of only four capacitances is enough; for instance, Cgg, where k stands for g, d, s, and b, i.e. top gate, drain, source and Cgd, Cdg, and Cdd can be chosen as the independent set. back-gate, respectively. The terminal currents, thus, can be obtained by either computing the time derivative of the Model validation corresponding terminal charge or by the weighted sum of the In order to validate the presented model, we perform the DC and time derivative of the terminal voltages, where the weights are RF measurements of an experimental monolayer MoS2-FET. The given by the intrinsic capacitances. fabricated device consists of an n-type channel of a chemical The intrinsic capacitances of FETs are modeled in terms of the vapor deposited (CVD) MoS2 monolayer transferred onto 285 nm terminal charges. Specifically, from the electrostatics given in Eq. intrinsic Si/SiO2 wafer. The 150-nm-long MoS2 channel is (1) the following relations are derived23: contacted with a stack of 2/70 nm Cr/Au and electrostatically Z L controlled by an embedded gate formed by a 10-nm barrier of Qgb ¼ Qg þ Qb ¼ W Qnet ðxÞdx; (7) atomic layer deposited Al2O3 and a gate metal stack consisting of 0 2/23 nm Ti/Au. More details on the fabrication and characteriza- Z L tion process can be found in the Methods section. Table 1 WCt Qg ¼ Q0  Qnet ðxÞdx; (8) summarizes the input parameters used for simulating the device Ctb 0 under test. The extracted 2D semiconductor–metal contact Z L resistance for the device is 3.5 kΩ µm and has been included in WCb Qb ¼ Q0  Qnet ðxÞdx; (9) the simulation by connecting lumped resistors to the source and Ctb 0 drain terminals. where Q0 = WLCtCb(Vg − Vg0 − Vb + Vb0)/Ctb. The charge con- We first test our model by comparing the DC transfer trolled by both the drain and source terminals is computed based characteristics (TCs) obtained at two different drain voltages. A on the Ward–Dutton’s linear charge partition scheme,24 which good agreement between both, measurements and simulations, guarantees charge conservation: has been achieved as shown in Fig. 2. The model predicts the DC Z L behavior accurately in all regimes of operation with current values Qd ¼ W x Qnet ðxÞdx; (10) ranging between 10−3 up to 102 µA/µm. However, the experi- 0 L mental device departs from the exponential trend for values in the Z L limit of the IRDS specification for low-power applications, being   x the OFF current actually limited by the onset of hole current at Qs ¼  Qg þ Qb þ Qd ¼ W 1  Qnet ðxÞdx: (11) 0 L negative Vgs (see Supplementary Notes and Supplementary Fig. S1 The above expressions can be conveniently written using u as for a detailed discussion). This small mismatch, however, does not the integration variable, as it was done to model the drain impact the dynamic operation prediction. Indeed, we have current in Eq. (5). Based on the fact that the drain current is the assessed the expected RF performance of such device in Fig. 3 same at any point x along the channel (i.e. we are under the by benchmarking the simulated small-signal current gain (h21) quasi-static approximation framework), we get from the transport and unilateral power gain (U) against the results extracted from model the following equations needed to evaluate the charges in Eqs. (7)–(11): Table 1. Input parameters of the 2DFET under test. μW dx ¼ Qtot ðuÞ dV dV dVc du Ids hR c du i: L 150 nm µ0 21.2 cm2/Vs μW u (12) x¼ Ids us Qtot ðuÞ dVc du du dV dVc W 10 µm m K 26 0.48m0 Lt 10 nm mQ 26 0.57m0 Replacing Eq. (12) in Eqs. (7) and (10), the following compact Lb 285 nm m0 9.11 × 10−31 kg expressions are obtained for the terminal charges Qgb and Qd: εt 9 gK27 2 2ð3Ctb ðeud ð1 þ us Þeus ð1 þ ud ÞÞ þ eus eud ðCdq þ Ctb Þðu3d  u3s ÞÞ Qgb ¼ Q2D 6Ctb ðeud  eus Þ þ 3eus eud ðCdq þ Ctb Þðu2d  u2s Þ εb 3.9 gQ27 6 ; (13) Vg0 0.42 V ΔE218 0.11 eV 2 3ud  5ud us þ 2us 5 3 2 5 Qd  Q2D 15 Vb0 0V Nit 1.8 × 1016 m−2 ðu2d  u2s Þ 2 T 300 K Vit 0.085 eV where Q2D = WLCdqVth. Equation (13) can be replaced in Eqs. (8), Published in partnership with FCT NOVA with the support of E-MRS npj 2D Materials and Applications (2019) 47 F. Pasadas et al. 4 Fig. 2 Transfer characteristics for different drain voltages in a linear and b logarithmic scales. Simulations are plotted with solid lines, and experimental measured data with symbols. Dashed lines in b highlight both the IRDS high-performance and low-power IOFF current limits. carriers and the device operates in the OFF state. This situation happens for overdrive gate biases lower than the threshold voltage, VA, according to Fig. 5e. Given the aforementioned conditions then Cgg ≈ CtCbWL/Ctb and Cgd ≈ Cdg ≈ Cdd ≈ 0, see to the left of A1 point in Fig. 5c. Saturation regime (ON operation): On the other hand, when Vcd > 10Vth while Vcs < 10Vth, the pinch-off is originated at the drain side. This situation is produced for overdrive gate biases between VA and VB in Fig. 5e (“A–B” section). Both Cgg (“A1–B3” section) and Cdg (“A1–B2” section) jump because the channel charge at the source side becomes very sensitive to the Fermi level location when it is close to the conduction band edge. However, Cgd and Cdd are negligible (“A1–B1” section) because the Fig. 3 Simulated (solid line) and measured (symbols) RF perfor- depletion region close to the drain prevents this terminal to mance of the MoS2-based FET described in Table 1 (Vgs = 4.4 V; control the channel charge. The saturation regime is also observed Vds = 3.5 V). The device shows a cut-off frequency fT = 20.2 GHz and at the right column of Fig. 5 for drain biases higher than VC (drain a maximum oscillation frequency fmax = 11.3 GHz. saturation voltage) in Fig. 5f (right of C point). The intrinsic capacitances Cgg (right of C3 point) and Cdg (right of C2 point), the experimental S-parameters (after de-embedding) measured in shown in Fig. 5d, decrease with respect to the linear regime (left of the range 0.1–15 GHz. Both, simulated h21 and U, are predicted C point, explained below) because the channel is depleted at the with excellent agreement to the experimental measurements. In drain side, so both Qg and Qd become less sensitive to Vgs as order to evaluate the RF performance, we calculate the intrinsic compared to the linear regime. On the other hand, Cgd and Cdd are capacitances, plotted in Fig. 4 (solid lines). The relative error negligible (right of C1 point), as Qg and Qd cannot be controlled between the numerical solution of Eq. (14) by using the anymore by the drain terminal after the depletion of the channel expressions in Eqs. (8)–(11) and the analytical computation of drain side, which is confirmed in Fig. 5b. Eq. (14) by using the compact expressions in Eq. (13) is less than Linear (ohmic) regime (ON operation): This regime takes place 2% for the bias window considered in Fig. 4. The results are when both Vcd and Vcs < 10Vth. This situation is produced for gate presented together with the intrinsic capacitances relying on the overdrive voltages higher than VB in Fig. 5e (right of B point), well-known conventional charge model developed for bulk where the channel starts to leave the depletion scenario at the MOSFETs11 and elsewhere used to model 2DFETs2. As can be drain side. Then a jump is observed in Cgg (right of B3 point), Cdg seen, the latter is accurate only either when a low drain bias is (right of B2 point), Cgd and Cdd (right of B1 point) as a applied or if the device is operated in the subthreshold regime consequence of the recovered electrical connection between (see Supplementary Notes and Supplementary Fig. S2 for more the channel and the drain terminal (see Fig. 5a, c). The linear details). regime can be also observed at the right column of Fig. 5 for drain The trends in the intrinsic capacitances can be better under- biases lower than VC (see Fig. 5f). The negative value of Vcs means stood looking at the overdrive gate and drain bias dependences of that the channel is degenerated at the source side for the specific both gate (Qg) and drain (Qd) charges, which are depicted in Fig. bias considered in this study. In Fig. 5d, it can be seen that Cgg (left 5a, b, respectively. Figure 5c, d shows the same bias dependence of C3 point), Cdg (left of C2 point), Cgd and Cdd (left of C1 point) of a set of four independent intrinsic capacitances of the 4T 2DFET decrease with Vds as the channel get closer to the drain depletion under test. As the device is an n-type transistor, we have also condition reached at Vds = VC. plotted the shift of the quasi-Fermi level with respect to the Finally, with the aim of showing the potential of the developed conduction band edge at both the drain/source sides (corre- TCAD tool, a relevant circuit commonly used to evaluate the sponding to the chemical potentials Vcd and Vcs) in Fig. 5e, f. For performance of a digital technology, namely, a ring oscillator (RO) the sake of clarity, we provide a separate discussion of the intrinsic is simulated. The design of a three-stage based RO encompasses capacitances according to the transistor operation regime. both DC and transient simulations. Each device has been Subthreshold regime (OFF operation): If both Vcd and Vcs > 10Vth, described by the parameters shown in Table 1 that have been then Qg, Qd ∼ 0 (see Fig. 5a). Therefore the channel is empty of demonstrated to accurately reproduce the fabricated MoS2-based npj 2D Materials and Applications (2019) 47 Published in partnership with FCT NOVA with the support of E-MRS F. Pasadas et al. 5 Fig. 4 Intrinsic capacitances versus a overdrive gate bias (at Vds = 1 V) and b drain bias (at Vgs – Vg0 = 3.4 V). Solid lines represent our model outcome and dashed lines show the data calculated using the model adopted in ref. 2 Fig. 5 Gate and drain charges versus a overdrive gate bias (at Vds = 1 V) and b drain bias (at Vgs – Vg0 = 3.4 V). Intrinsic capacitances versus c overdrive gate bias (at Vds = 1 V) and d drain bias (at Vgs – Vg0 = 3.4 V). Shift of the Fermi level with respect to the conduction band edge, namely, the chemical potential at the drain (Vcd) and source (Vcs) sides versus e overdrive gate bias (at Vds = 1 V) and f drain bias (at Vgs – Vg0 = 3.4 V). voltage gain of 3.7 at fosc, upon biasing it at Vgs = 1.25 V and Vds = 3.5 V. Figure 6 shows how the technology assessed in this work provides a suitable switching characteristic around 1 GHz. The simulation predicts a distorted sinusoidal as the AC component goes over a large range of bias with imperfect linearity. It is worth noticing that a small-signal model (in contrast with a large-signal model) could not predict that feature. Supplementary Fig. S3 provides a comparison of the compact model outcome against experimental measurements of bilayer MoS2 FETs26 comprising the assessment of transfer characteristics, output characteristics, the performance of an inverter, and a five-stage ring oscillator based on such devices, the latter validating the large-signal prediction capability of the model. DISCUSSION Fig. 6 Three-stage ring oscillator switching at a frequency around 1 GHz based on the 2DFETs described in Table 1. The supply bias is A physics-based large-signal compact model of four-terminal 2D 3.5 V. semiconductor-based FETs, implemented in Verilog-A, has been presented. The model captures the terminal charges and capacitances covering all the operation regimes, so accurate time FET in Figs. 2 and 3. Specifically, we have designed the three-stage domain simulations and frequency response studies at the circuit RO to oscillate at a specific frequency fosc = 31/2/(2πRddC) ≈ 1 GHz level are feasible within the validity of the quasi-static approxima- by using a resistor connected to each drain of Rdd = 20.4 kΩ and tion. The model can be incorporated to existing commercial circuit capacitors connected to the output of each stage with C = 13.5 fF. simulators enabling the simulation of digital and RF applications In doing so, each single stage has been designed to show a based on emerging 2D technologies. We have checked that the Published in partnership with FCT NOVA with the support of E-MRS npj 2D Materials and Applications (2019) 47 F. Pasadas et al. 6 model outcome is consistent with our experimental measure- 4. Rakheja, S. et al. An ambipolar virtual-source-based charge-current compact model ments of MoS2-FET devices targeting RF applications. Finally, a for nanoscale graphene transistors. IEEE Trans. Nanotechnol. 13, 1005–1013 (2014). design of a three-stage ring oscillator has been carried out to 5. Jiménez, D. Drift-diffusion model for single layer transition metal dichalcogenide exhibit the potential of the TCAD tool presented and showing the field-effect transistors. Appl. Phys. Lett. 101, 243501 (2012). 6. Parrish, K. N., Ramón, M. E., Banerjee, S. K. & Akinwande, D. A Compact model for feasibility of using this technology in switching applications in the graphene FETs for linear and non-linear circuits. In 17th International Conference gigahertz range. on Simulation of Semiconductor Processes and Devices. SISPAD, Denver, CO, USA, 75–78 (2012). 7. Yadav, C., Rastogi, P., Zimmer, T. & Chauhan, Y. S. Charge-based modeling of METHODS transition metal dichalcogenide transistors including ambipolar, trapping, and Fabrication negative capacitance effects. IEEE Trans. Electron Devices 65, 4202–4208 (2018). The MoS2 FET reported in this paper belongs to the same batch as the 8. Taur, Y., Wu, J. & Min, J. A short-channel I-V model for 2-D MOSFETs. IEEE Trans. devices published in ref. 27 by some of the authors. The fabrication process Electron Devices 63, 2550–2555 (2016). begins with patterning two embedded gate fingers on intrinsic Si/SiO2 9. Rahman, E., Shadman, A., Ahmed, I., Khan, S. U. Z. & Khosru, Q. D. M. A physically (>20 kΩ cm). Then, the embedded 150-nm gate metal stack consisting of based compact I–V model for monolayer TMDC channel MOSFET and DMFET 2/23 nm Ti/Au was defined and deposited by using electron beam biosensor. Nanotechnology 29, 235203 (2018). lithography (EBL) and e-beam evaporation. Large area atomic single layer 10. Gholipour, M., Chen, Y.-Y. & Chen, D. Compact modeling to device- and circuit- CVD MoS2, grown by a standard vapor transfer process as described in level evaluation of flexible TMD field-effect transistors. IEEE Trans. Comput. Des. ref. ,27 was then transferred by poly(methyl methacrylate)-assisted wet Integr. Circuits Syst. 37, 820–831 (2018). transfer. Phosphoric acid etching was used to connect the embedded gate 11. Tsividis, Y. Operation and Modeling of the MOS Transistor (Oxford: Oxford Uni- fingers and the gate pad. The active MoS2 channel was etched using Cl2/O2 versity Press, New York, 1999). plasma. Finally, source and drain (S/D) contacts consisting of 2/70 nm Cr/ 12. Marin, E. G., Bader, S. J. & Jena, D. A new holistic model of 2-D semiconductor Au were patterned through a final EBL step. FETs. IEEE Trans. Electron Devices 65, 1239–1245 (2018). 13. Grasser, T. Stochastic charge trapping in oxides: from random telegraph noise to bias temperature instabilities. Microelectron. Reliab. 52, 39–70 (2012). Electrical measurements 14. Illarionov, Y. Y. et al. The role of charge trapping in MoS2/SiO2 and MoS2/hBN The electrical DC characterization was done on a Cascade Microtech field-effect transistors. 2D Mater. 3, 035004 (2016). Summit 11000B-AP probe-station using an Agilent B1500A parameter 15. Knobloch, T. et al. A physical model for the hysteresis in MoS 2 transistors. IEEE J. analyzer. Microwave performance was characterized using an Agilent two- Electron Devices Soc. 6, 972–978 (2018). port vector network analyzer (VNA-E8361C). All measurements were taken 16. Cao, W., Kang, J., Bertolazzi, S., Kis, A. & Banerjee, K. Can 2D-nanocrystals extend at room temperature, in ambient atmosphere, and in the dark. The intrinsic the lifetime of floating-gate transistor based nonvolatile memory? IEEE Trans. microwave performance is obtained after de-embedding the measured Electron Devices 61, 3456–3464 (2014). data using OPEN and SHORT structures. The OPEN de-embedding was 17. Ma, N. & Jena, D. Carrier statistics and quantum capacitance effects on mobility performed on the as-measured device-under-test by etching away the extraction in two-dimensional crystal semiconductor field-effect transistors. 2D MoS2 in the active regions. The SHORT de-embedding is subsequently Mater. 2, 015003 (2015). carried out by depositing a strip of metal across the channel region, 18. Kormányos, A. et al. k · p theory for two-dimensional transition metal dichalco- shorting out all pads. genide semiconductors. 2D Mater. 2, 022001 (2015). 19. Rasmussen, F. A. & Thygesen, K. S. Computational 2D materials database: elec- tronic structure of transition-metal dichalcogenides and oxides. J. Phys. Chem. C Circuit simulations 119, 13169–13183 (2015). The developed large-signal model of 4T 2DFETs is implemented in Verilog- 20. Kadantsev, E. S. & Hawrylak, P. Electronic structure of a single MoS2 monolayer. A and included as a separate module in Keysight© Advanced Design Solid State Commun. 152, 909–913 (2012). System (ADS), a popular electronic design automation software for RF and 21. Landauer, G. M., Jiménez, D. & González, J. L. An accurate and Verilog-A com- microwave applications. It calculates the electrostatics by iteratively patible compact model for graphene field-effect transistors. IEEE Trans. Nano- solving Eqs. (1) and (3) during run-time using a construct,21,22 and technol. 13, 895–904 (2014). computes the static and dynamic response of the device by evaluating Eqs. 22. Deng, J. D. J. & Wong, H.-S. P. A compact SPICE model for carbon-nanotube field- (5) and (6), respectively, using the compact expressions derived in effect transistors including nonidealities and its application—Part I: model of the this work. intrinsic channel region. IEEE Trans. Electron Devices 54, 3186–3194 (2007). 23. Pasadas, F. & Jiménez, D. Large-Signal model of graphene field-effect transistors —Part I: Compact modeling of GFET intrinsic capacitances. IEEE Trans. Electron DATA AVAILABILITY Devices 63, 2936–2941 (2016). The data that support the findings of this study are available from the corresponding 24. Ward, D. E. & Dutton, R. W. A charge-oriented model for MOS transistor capaci- author upon reasonable request. tances. IEEE J. Solid-State Circuits 13, 703–708 (1978). 25. Pasadas, F. & Jimenez, D. Erratum to “large-signal model of graphene field-effect transistors—Part I: Compact modeling of GFET intrinsic capacitances” [Jul 16 CODE AVAILABILITY 2936-2941]. IEEE Trans. Electron Devices 66, 2459–2459 (2019). 26. Wang, H. et al. Integrated circuits based on bilayer MoS 2 transistors. Nano Lett. The large-signal model of 2DFETs implemented in Verilog-A is available from the 12, 4674–4680 (2012). corresponding author upon reasonable request. 27. Sanne, A. et al. Embedded gate CVD MoS2 microwave FETs. npj 2D Mater. Appl. 1, 26 (2017). Received: 2 July 2019; Accepted: 13 November 2019; ACKNOWLEDGEMENTS The authors would like to thank the financial support of Spanish Government under projects TEC2017-89955-P (MINECO/AEI/FEDER, UE), TEC2015-67462-C2-1-R REFERENCES (MINECO), and RTI2018-097876-B-C21 (MCIU/AEI/FEDER, UE). F.P. and D.J. also 1. Choi, W. et al. Recent development of two-dimensional transition metal dichal- acknowledge the support from the European Union’s Horizon 2020 Research and cogenides and their applications. Mater. Today 20, 116–130 (2017). Innovation Program under Grant Agreement No. 785219 GrapheneCore2. A.G. 2. Suryavanshi, S. V. & Pop, E. S2DS: physics-based compact model for circuit acknowledges the funding by the Consejería de Economía, Conocimiento, Empresas simulation of two-dimensional semiconductor devices including non-idealities. J. y Universidad de la Junta de Andalucía and European Regional Development Fund Appl. Phys. 120, 1–10 (2016). (ERDF), ref. SOMM17/6109/UGR. E.G.M. gratefully acknowledges Juan de la Cierva 3. Han Wang, Hsu, Jing Kong, A., Antoniadis, D. A. & Palacios, T. Compact virtual- Incorporación IJCI-2017-32297 (MINECO/AEI). A.T.-L. acknowledges the FPU program source current–voltage model for top- and back-gated graphene field-effect (FPU16/04043). D.A. acknowledges the Army Research Office for partial support of transistors. IEEE Trans. Electron Devices 58, 1523–1533 (2011). this work, and the NSF NASCENT ERC and NNCI programs. npj 2D Materials and Applications (2019) 47 Published in partnership with FCT NOVA with the support of E-MRS F. Pasadas et al. 7 AUTHOR CONTRIBUTIONS Reprints and permission information is available at http://www.nature.com/ F.P. and D.J. performed the development of the analytic model and the Verilog-A reprints implementation. F.P., E.G.M., A.T.-L., and F.G.R. contributed to perform and interpreting the simulations. A.G. and D.J. overall supervised the compact model Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims development and analyzed the results. S.P. performed the synthesis and in published maps and institutional affiliations. characterization of the MoS2 films, as well as performed the design conception, fabrication, and measurements of the MoS2 transistors under the direction and supervision of D.A. F.P., and D.J. wrote the manuscript. F.P., E.G.M., F.G.R., A.G., D.A., and D.J. contributed to the scientific discussions. All authors revised and approved Open Access This article is licensed under a Creative Commons the final manuscript. Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party COMPETING INTERESTS material in this article are included in the article’s Creative Commons license, unless The authors declare no competing interests. indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly ADDITIONAL INFORMATION from the copyright holder. To view a copy of this license, visit http://creativecommons. Supplementary information is available for this paper at https://doi.org/10.1038/ org/licenses/by/4.0/. s41699-019-0130-6. Correspondence and requests for materials should be addressed to F.P. © The Author(s) 2019 Published in partnership with FCT NOVA with the support of E-MRS npj 2D Materials and Applications (2019) 47