This is the accepted version of the article: Diaz-Fortuny, Javier; Martin Martinez, Javier; Rodriguez, Rosana; [et al.]. «A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models». Solid-State Electronics, Vol. 159 (Sep. 2019), p. 99-105. DOI 10.1016/j.sse.2019.03.045 This version is available at https://ddd.uab.cat/record/249165 under the terms of the license A Smart Noise- and RTN-Removal Method for Parameter Extraction of CMOS Aging Compact Models Javier Diaz-Fortuny1*, Javier Martin-Martinez1, Rosana Rodriguez1, Rafael Castro-Lopez2, Elisenda Roca2, Francisco V. Fernandez2 and Montserrat Nafria1. 1 Electronic Engineering Department, (REDEC) group. Universitat Autònoma de Barcelona (UAB), Barcelona 08193, (Spain). 2 Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, (Spain). *corresponding author: javier.diaz@uab.es Abstract—In modern nanometer-scale CMOS technologies, Another important aspect is that an accurate extraction time-zero (TZV) and time-dependent variability (TDV) method of the defect parameters requires statistical effects, e.g., coming from aging mechanisms like Bias characterization of transistors under accelerated stress Temperature Instability (BTI), Hot Carrier Injection conditions [9]. Conventional BTI/HCI aging characterization (HCI) or Random Telegraph Noise (RTN), have re- techniques are based in the application of serialized stress- emerged as a serious threat affecting the performance of measurement (SM) sequences to one or few transistors analog and digital integrated circuits. Variability induced simultaneously by using probe stations. The SM by the aging phenomena can lead circuits to a progressive characterization technique consists in an stress phase, which accelerates the device degradation through the application of malfunction or failure. In order to understand the effects overvoltage to the device terminals, and a measurement phase, of the mentioned variability sources, a precise statistical where the effects of the induced aging can be measured in characterization and modeling of these effects should be reasonable testing times [10]. However, to get sufficient done. Typically, transistor TDV characterization entails statistical data, a massive aging test, with hundreds of long, and typically prohibitive, testing times, and huge transistors subjected to the same characterization pattern, must amounts of data, which are complex to post-process. This be performed. Doing so serially (one device at a time) may, work presents a new method to statistically characterize however, take several months. In our work, we use our the emission times and threshold voltage shifts (∆Vth) previously designed 65-nm array-based IC ENDURANCE chip related to oxide defects in nanometer CMOS transistors [11] in combination with a custom-designed characterization during aging tests. The method identifies the Vth drops setup [12] that allows to execute BTI/HCI aging tests over associated to oxide trap emissions during BTI and HCI hundreds of CMOS transistors with a stress parallelization aging recovery traces while removing RTN and technique that significantly reduces the total aging test time. background noise contributions, to avoid artifacts during The impact of aging can be modeled through the analysis of data analysis. the emission time (τe) and corresponding impact on the variation of the threshold voltage (η) of each defect in the Keywords—CMOS; BTI; HCI; parameters; extraction; method; transistor. This analysis is carried out during the measurement RTN; defects; aging; phases, after the application of overvoltage stress, where a I. INTRODUCTION ‘recovery’ of the device threshold voltage Vth can be observed [13]. Fig. 1 shows experimental recovery traces attained after With nowadays CMOS technology downscaling, BTI [1][2] the execution of a massive BTI test, where charge detrapping and HCI [3][4] aging effects, as well as RTN [5][6] transient from oxide defects can be clearly seen during the recovery time effects, have re-emerged as important time-dependent as positive abrupt current jumps (i.e., Vth decrease). Note also variability (TDV) phenomena that must be taken into account in the design of digital and analog integrated circuits (ICs). During circuit operation, the variability effects related to the trapping/detrapping in/from oxide defects could result in circuit malfunction due to the shift of some transistor parameters, such as the threshold voltage (Vth) [7]. Thus, it is critical for IC designers to take into account TDV effects to implement reliability-aware circuits [8]. To this end, appropriate TDV compact models, like the Probabilistic Defect Occupancy (PDO) model [3], are essential. These models need to account for and clearly distinguish the ‘slow’ defects, responsible for aging-induced degradation, from the ‘fast’ defects causing the RTN transient variations. As shown in this paper, isolating the impact of the different types of defects within the experimental Fig. 1. Several recovery traces from a massive BTI test showing discrete data is not straightforward. current increments. in Fig. 2 that the simultaneous presence of RTN in the traces could mask or significantly increase the current increments, so it is critical to distinguish between those current levels that are linked to fast transients and slow defect discharges. In this work, we introduce a novel and smart method of defect parameters extraction that identifies the defect-related τe and η values from a large number of experimental transistor recovery traces, where fast defect capture/emissions (i.e., RTN) and background noise are present. To model the effect of aging without noise-masking issues, the defect parameters extraction method removes the RTN and background noise from the measured BTI/HCI recovery traces and evaluates the {τe, η} tuple of each slow defect discharge found. Fig. 3. Diagram flow of the parameters extraction method. Moreover, as can be observed in the recovery trace, fast transitions associated to RTN are present during the entire Fig. 2. Zoom-in of some traces in Fig. 1 showing fast defect transitions characterization experiment. The inset of Fig. 4 exposes one of (RTN) mixed with slow defect discharges that result in I DS abrupt jumps. those fast defect transitions between two separated ∆Vth levels superimposed to a temporaly constant ∆Vth level. Fig. 4(b) reveals fast capture/emission transitions, switching between 4 II. DESCRIPTION OF THE METHOD different ∆Vth levels (i.e., L0 to L3) and mixed with The defect parameters extraction method follows the flow background noise. A visual inspection of Fig. 4(b) reveals the diagram shown in Fig. 3. For each device involved in the aging joint contribution of tow individual RTN signals, one test, the method treats each recovery trace individually. First, it switching between ∆Vth levels L0-L1 and the other one converts the IDS vs. time traces measured after the stress period switching with lower capture/emission times between L1-L3 into the equivalent ∆Vth vs. time trace (the difference between and between L0-L2. the instantaneous threshold voltage and that of the fresh device). By means of the Weighted Time Lag Plot (WTLP) method [5][6], all ∆Vth levels of the trace are obtained. In order to remove the background noise from the recovery traces, each experimental ∆Vth sample is assigned to one of the ∆Vth levels previously found with the WTLP method, quantizing the trace and removing the background noise. Then, all RTN fast defect transitions (if any) are removed from the trace through the analysis of each transition between the i-th and the (i+1)-th recovery sample. The last step consists in the extraction of τe and η parameters associated to each of the identified defect discharge. This 5-step procedure is described in detail in the following. 1) IDS conversion to ∆Vth. For each tested device, the IDS recovery traces measured as a function of time during the aging test is converted into the equivalent ∆Vth vs. time trace by means of the pre-stress IDS-VGS curve, i.e., the IDS-VGS curve of the fresh device [14]. For instance, Fig. 4 shows the results of the conversion from a measured IDS trace, like the Fig. 4. (a) Example of a ∆Vth trace constructed from the measured IDS ones represented in Fig. 1, to its equivalent ∆Vth waveform, recovery data, showing three clear slow defect discharges labeled with green where 3 charge emissions (denoted with green arrows) can be arrows. The inset in figure (a) shows RTN and background noise on top of a clearly located during the measurement time window of 100s. ∆Vth level. (b) Zoom-in in Figure (a) showing the combination of two fast defects. 2) Identification of ∆Vth trace levels. The next step consists in the application of the WTLP method [5][15] to each recovery trace, in order to identify the number and magnitude of the ∆Vth levels present in the trace. The basic principle of the WTLP technique is the Time Lag-Plot (TLP) method [16], in which the i-th data sample of an experimental signal is represented versus the (i+1)-th data sample as shown in Fig. 5(a). The plot diagonal shows populated data regions corresponding to different data levels (i.e., IDS or ∆Vth) while transitions between different levels and background noise are located outside the diagonal. The TLP methodology can be used when the background noise is low enough, so that the ∆Vth levels and/or transitions Fig. 5. Representation of a conventional TLP in an arbitrary example (a) and can be clearly distinguished. However, if the background noise the corresponding WTLP in (b) [5]. is so relevant that masks the capture/emission transitions, the resulting TLP of the ∆Vth levels are overlapped with the For instance, Fig. 6(a) shows the WTLP resulting from the background noise making impossible to accurately locate analysis of trace 1 in Fig. 4(a). In this case, the corresponding them. Thus, the improved WTLP [5] is used instead of the ∆Vth variations have been calculated from the comparison TLP to clearly separate the background noise present in the between the fresh IDS-VGS and the IDS current measured after recovery traces from the capture/emission defect transitions. the BTI stress, as explained in step 1. By analyzing the The WTLP represents the probability that a (∆Vth-i – ∆Vth–(i+1)) diagonal of the WTLP, four groups of populated data regions, data sample in a recovery trace corresponds to one of the separated in the figure by green dashed arrows, can be levels present in the trace. This probability is calculated by the distinguished. Each one of the data groups corresponds to a normal bivariate distribution function (1.1) for each data different ∆Vth level present in the recovery trace. Transitions sample. The weigthed time lag function defined in equation from one data group to the next one are considered as slow (1.2) reveals the contribution of all samples in the recovery defect emissions at a specific τe and the difference between trace, weighted by its distance to the analyzed ∆Vth-i data two ∆Vth levels corresponds to the η of the discharged defect. sample. Furthermore, when present, fast capture/emissions on top of    I  x    I  y 2   each ∆Vth level can also be clearly distinguished, as red-colored  i (x, y)  1 exp   i   i 1   (1.1) regions in the diagonal (i.e., in the ∆Vth levels L0 to L9) with 2 2  2 2  other less populated regions located perpendicularly to the   diagonal (i.e., ∆Vth level transitions). Moreover, the ten red N 1 populated regions in the WTLP in Fig. 6(a) can be easily (x, y)  K  i (1.2) associated with each ∆Vth level present in the recovery trace in i 1 Fig. 6(b) (pointed out with red arrows). As shown in Fig. 5(b), where the function  has been plotted against all data samples of the TLP Fig. 5(a), the  In order to clearly see the ∆Vth values associated to the function gets higher values in the most populated regions of RTN transitions detected in Fig. 4(b), a zoom-in of the WTLP the TLP. Moreover, those populated regions are located across (red square in Fig. 6(a)) is plotted in Fig. 7. The zoom clearly the main diagonal of the WTLP where each local maximum shows the 4 red regions across the diagonal, which correspond corresponds to an individual current level present in the to the four different ∆Vth levels (i.e., L0, L1, L2 and L3). The recovery trace. blue regions out of the diagonal in the WTLP indicate the Fig. 6. (a) WTLP resulting from the analysis of Trace #1 in Fig. 4(a). Corresponding ∆Vth level in the recovery trace for each red-colored zone in the WTLP in (a). transitions between levels (e.g., L1  L3). For instance, for t~25s, the signal switches between levels L1 and L3 and later, for t~30s, the signal switches between L0 and L2. These levels result from the joint combination of the two individual RTN signals shown in Fig. 4 (b), coming from the fast charges/discharges of two oxide defects. The results shown in Fig. 7 clearly demonstrate that the application of the WTLP to the ∆Vth recovery trace allows an accurate location of all ∆Vth levels, and is able to distinguish between RTN and BTI contributions. Fig. 7. Zoom-in of the WTLP in Fig. 6(a) showing, for the two RTN signals Fig. 8. (a) Recovery traces (blue) with the reconstructed trace without noise in Fig. 4(b), the ∆Vth levels in the diagonal of the WTLP and the (red). (b), (c) zoom in the signals showing RTN (blue traces) and trace corresponding transitions between ∆Vth levels outside the diagonal. reconstruction without background noise (red traces). 3) Background noise removal. Once the ∆Vth levels  Case (iii): Defect discharging. The (i-th)+1 ∆Vth level is are identified with the WTLP method, the procedure assigns smaller than the i-th ∆Vth level. For instance, two the closest ∆Vth level to each sample in the ∆Vth trace. This consecutive ∆Vth samples switching from level L3 to L1. step quantizes the ∆Vth recovery trace, removing the background noise and keeping only ∆Vth levels associated to To construct the TM, the ∆Vth recovery trace is swept by captures/emissions of RTN and BTI contributions. For its (ii, ii+1) elements and the transition location counter of instance, Fig. 8(a)-(c) displays three ∆Vth traces (blue traces), the TM initial-final ∆Vth level is incremented when showing high ∆Vth degradation due to the previous stress, and needed. Case (i) transitions will lay in the main diagonal of also the ∆Vth trace reconstruction (red traces) with the the TM while case (ii) and case (iii) transitions will be background noise removed. During the recovery period (in located above and below the TM main diagonal this example, from 2ms to 100s), different ∆Vth levels can be respectively. For instance, in Trace 1 in Fig. 8(a), which is observed because of defect emissions mixed with RTN actually the same trace in Fig. 4(a), ten ∆Vth levels have phenomena, as shown in detail in the zoom-in plots in Fig. been detected by the WTLP method (Fig. 6(a)). The 8(b) and (c). resulting 10x10 TM is filled with all ∆Vth transitions identified during the ∆Vth recovery trace sweep as shown 4) Removal of RTN-related transients. In order to in Fig. 9(a). In order to remove fast RTN transitions from distinguish between RTN and BTI contributions, we define a the traces, the method analyzes the data in the TM, square matrix, named Transition Matrix (TM), to store the distinguishing the following two cases: transitions between different ∆Vth levels in the recovery trace. The dimention of the TM is the total number of ∆Vth levels  Slow emission recognition: This type of defect emissions found, in this particular case ten, each ∆Vth level is denoted as is characterized by a unique defect discharge to a lower LN where N ranges from 0 to 9. The rows of the TM are ∆Vth level. In the TM, this appears as a ‘1’ in the defined as the initial ∆Vth levels (i.e., i-th ∆Vth level) while corresponding element below the TM main diagonal, and a the columns are defined as the final ones (i.e., (i+1)-th ∆Vth ‘0’ in the TM symmetric position. Analyzing the TM in level). During the ∆Vth trace analysis, three different ∆Vth Fig. 9(a), three different emissions, without any further level transitions can be distinguished: capture, can be found marked with blue circles: from initial to final ∆Vth levels L4-L3, L6-L4 and L8-L7.  Case (i): No change of the ∆Vth level, i.e., the ∆Vth level of the i-th data sample equals the (i+1)-th ∆Vth level. For  Transients recognition: the method identifies multiple and instance, two consecutive ∆Vth samples staying at level consecutive transitions between two distinct ∆Vth levels. L1. For instance, all transitions of the combined RTN signals in Fig. 4(b), uncoupled by the WTLP method in Fig. 7(b),  Case (ii): Defect charging. The (i+1)-th ∆Vth level is are marked in the TM of Fig. 9(a) with a green dashed larger than the i-th ∆Vth level. For instance, two square, which correspond to transitions from/to levels L0 consecutive ∆Vth samples switching from level L1 to L3. to L3. A clear example of a transient in the TM is highlighted with a solid red square box, which corresponds to the RTN signal shown in the inset of Fig. 4(a). The main diagonal (of the red square box) indicates the number of samples at the same ∆Vth level (i.e., initial and final ∆Vth levels L6 or L7) while hundred ten defect discharges (i.e., initial L7 to final L6) and 109 defect charges (i.e., initial L6 to final L7) take place in the RTN signal. Fig. 10 displays the resulting 1, 2 and 3 traces after the application of the methodology showing a total of 3, 8 and 4 slow emissions, without artifacts coming from fast defect Fig. 10. Filtered recovery traces without noise and RTN ready for defect transitions and background noise, respectively. parameter extraction. 5) Defect parameters extraction. The last step consists in obtaining the τe and η parameters of the slow defect III. METHOD VALIDATION emissions. This is done by locating the elements below the In order to evaluate the validity of the described parameter TM main diagonal showing single discharge that have a extraction method, BTI or HCI recovery data can be used. symmetrical zero above the TM main diagonal. The η value of Here, four individual BTI tests, each one involving 248 CMOS each detected defect is obtained by subtracting the final ∆Vth transistors with 8 different channel sizes (i.e., W and L), have from the initial ∆Vth. To allow the evaluation of the τe been considered for defect parameter extraction. Fig. 11 shows associated to the defect, when the TM is constructed, also the a schematic representation of the measurement setup [12] used times at which (ii, ii+1) transitions occur are saved. When a for the characterization of the ENDURANCE chip devices with slow discharge is encountered, the τe is assigned to the the following list of items: computed η value so it the defect is characterized by the tuple {τe, η}.  A full-custom printed circuit board (PCB), where the ENDURANCE IC chip is inserted for DUT measurements.  The Keysight Semiconductor Parameter Analyzer (SPA) model B1500A.  Agilent E3631A power supply for PCB and IC biasing.  T-2650BV Thermonics precision temperature system.  A USB Digital Acquisition System (DAQ), model USB- 6501 from National Instruments.  A personal computer (PC) equipped with Microsoft Windows® operating system and Matlab® software, both using 64-bits architecture. The Agilent E3631A power supply, the Keysight B1500A SPA and the Thermonics temperature system T-2650BV instruments are connected using an IEEE 488 General Purpose Interface Bus (GPIB), in order to send and receive data during Fig. 9. (a) TM corresponding to trace 1. The green dashed box define case (i), (ii) and (iii) transitions of the joint RTN in Fig. 4(b) while the red solid box define the transitions of the fast defect switching shown in the inset in Fig. 4(a). Blue circles indicate the location of slow defect emissions and the main diagonal is highlighted with a grey dashed line. (b) Illustrative example Fig. 11. Schematic representation of the instrumentation and their of the two ∆Vth level transitions in the RTN signal in the inset in Fig. 4(a). interconnections integrated into the measurement setup. tests executions. For the communication with the USB-6501 recovery traces before the slow emissions identification, a large DAQ, a USB 3.0 connection is used. number of ‘false’ events (with equal ∆Vth value as the RTN amplitude) would have been taken into account during the <η> During the BTI experiments, each device has been tested calculation. Therefore, the resulting <η> value, for all tested using a 6-cycle SM scheme, in which the duration of the stress geometries, would have been close to the ∆Vth of the fastest phases is increased logarithmically (i.e., 1s, 10s, 100s, 1000s RTN, masking the actual <η> of the BTI-related defects. Fig. 10,000s and 100,000s), while the measurement (i.e., recovery) 13 (b) also shows that η is exponentially distributed. The phase time always lasts 100s. During the stress period, a gate- results are in agreement with those in the literature [1], which source voltage VGS has been applied maintaining the drain- supports the validity of the methodology. source voltage VDS at 0V (four different VGS voltages have been considered), while for measurements VGS ≈ Vth and VDS = 100mV. The total test time required for a 6-cycle SM test on a single device takes 111,111s + (6·100s) = 111,711s ≈ 31 hours. Thus, for the four BTI tests involving 992 devices, the total test time, with conventional serial testing procedures, would be ≈ 3.5 years, a considerably large, and prohibitive, test time. In this work, and thanks to the array-based IC chip ad-hoc design, in order to significantly reduce the total testing time, the stress phases of each BTI test have been parallelized, without overlapping the measurement phases of any device. In this case, the testing time is reduced to only sixty-four hours per BTI test, resulting in a 4-BTI test that only lasts ten days, a significant test time reduction when compared to conventional serial testing. From the automated analysis of the data, a total of 10,582 slow emissions have been identified. Fig. 12 shows the histogram plots of the extracted τe from the defects found (a) (b) during the recovery traces showing that charges are emitted during the very first moments of the recovery phase. Fig. 12 also indicates increasing VGS voltage during the stress results in an increasing number of slow emissions. Fig. 13 shows the Fig. 13. (a) Distribution of the <η> values of the slow emissions as a function of the transistor area. (b) Exponential distribution of the η values, with statistical results obtained from the analysis of all {τe, η} tuples exponential fitting extracted from the four 6-cycle BTI tests for each tested extracted by using the method detailed in this work. Fig. 13 (a) geometry. shows the dependence of the <η> value on the transistor area. The results demonstrate that <η> decreases with the transistor area. If the RTN related transients were not removed from the CONCLUSION In this paper, a smart methodology for the massive extraction of CMOS aging parameters has been presented. In order to reduce the testing time required for the massive analysis of the aging of nanometer MOSFETS (from years to days), our fabricated array-based IC chip in combination with a stress parallelization technique have been used. Our method analyzes the BTI/HCI aging recovery traces and looks for ∆Vth voltage drops related to slow emissions after the application of accelerated stress patterns. The method identifies and removes the fast transient capture/emissions (RTN) and the background noise in the recovery traces to avoid artifacts during the CMOS defect parameters extraction. In the application example, the described method has allowed to extract the {τe, η} tuples of more than 10,000 defects emissions that can be used as input parameters to stochastic aging compact models. ACKNOWLEDGEMENTS This work has been supported in part by the TEC2013- 45638-C3-R and TEC2016-75151-C3-R Projects (funded by the Spanish Ministerio de Economia, Industria y Competitividad and ERDF). Javier Diaz Fortuny research activity has been supported by the FPI grant BES-2014- 067855. Fig. 12. τe histogram plots found during recovery analysis for the 80nm/60nm transistor geometry after 10,000s of pure BTI stress at four different VGS stress voltages. REFERENCES [9] Kaczer B, Grasser T, Roussel J, Martin-Martinez J, O’Connor R, O’Sullivan BJ, et al. Ubiquitous relaxation in BTI stressing-new [1] Kaczer B, Grasser T, Roussel PJ, Franco J, Degraeve R, Ragnarsson LA, evaluation and insights. Proc. Int. Reliab. Phys. Symp., IEEE; 2008, p. et al. Origin of NBTI variability in deeply scaled pFETs. IEEE Int 20–7. doi:10.1109/RELPHY.2008.4558858. Reliab Phys Symp Proc 2010:26–32. doi:10.1109/IRPS.2010.5488856. [10] Maricau E, Gielen G. Analog IC Reliability in Nanometer CMOS. New [2] Gao R, Manut AB, Ji Z, Ma J, Duan M, Zhang JF, et al. Reliable Time York, NY: Springer New York; 2013. doi:10.1007/978-1-4614-6163-0. Exponents for Long Term Prediction of Negative Bias Temperature Instability by Extrapolation. IEEE Trans Electron Devices [11] Diaz-Fortuny J, Martin-Martinez J, Rodriguez R, Nafria M, Castro- 2017;64:1467–73. doi:10.1109/TED.2017.2669644. Lopez R, Roca E, et al. A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging. Proc. [3] Martín-Martínez J, Gerardin S, Amat E, Rodríguez R, Nafría M, 14th Int. Conf. Synth. Model. Anal. Simul. Methods Appl. to Circuit Aymerich X, et al. Channel-hot-carrier degradation and bias temperature Des., 2017. doi:10.1109/SMACD.2017.7981600. instabilities in CMOS inverters. IEEE Trans Electron Devices 2009;56:2155–9. doi:10.1109/TED.2009.2026206. [12] Diaz-Fortuny J, Martin-Martinez J, Rodriguez R, Nafria M, Castro- Lopez R, Roca E, et al. TARS: A toolbox for statistical reliability [4] Duan M, Zhang JF, Ji Z, Zhang WD, Kaczer B, Asenov A. Key Issues modeling of CMOS devices. Proc. 14th Int. Conf. Synth. Model. Anal. and Solutions for Characterizing Hot Carrier Aging of Nanometer Scale Simul. Methods Appl. to Circuit Des., 2017. nMOSFETs. IEEE Trans Electron Devices 2017;64:2478–84. doi:10.1109/SMACD.2017.7981601. doi:10.1109/TED.2017.2691008. [13] Grasser T, Reisinger H, Wagner P-J, Schanovsky F, Goes W, Kaczer B. [5] Martin-Martinez J, Diaz J, Rodriguez R, Nafria M, Aymerich X. New The time dependent defect spectroscopy (TDDS) for the characterization Weighted Time Lag Method for the Analysis of Random Telegraph of the bias temperature instability. Proc. IEEE Int. Reliab. Phys. Symp Signals. IEEE Electron Device Lett 2014;35:479–81. (IRPS)., 2010, p. 16–25. doi:10.1109/IRPS.2010.5488859. doi:10.1109/LED.2014.2304673. [14] Kaczer B, Grasser T, Roussel PJ, Martin-Martinez J, O’Connor R, [6] Maestro M, Diaz J, Crespo-Yepes A, Gonzalez MB, Martin-Martinez J, O’Sullivan BJ, et al. Ubiquitous relaxation in BTI stressing-new Rodriguez R, et al. A new high resolution Random Telegraph Noise evaluation and insights. Proc Int Reliab Phys Symp 2008:20–7. (RTN) characterization method for resistive RAM. EUROSOI-ULIS doi:10.1109/RELPHY.2008.4558858. 2015 2015 Jt. Int. EUROSOI Work. Int. Conf. Ultim. Integr. Silicon, vol. 115, IEEE; 2015, p. 133–6. doi:10.1109/ULIS.2015.7063791. [15] Maestro M, Diaz J, Crespo-Yepes A, Gonzalez MB, Martin-Martinez J, Rodriguez R, et al. New high resolution Random Telegraph Noise [7] Mahapatra S, Parihar N. A review of NBTI mechanisms and models. (RTN) characterization method for resistive RAM. Solid State Electron Microelectronics Reliability 2018;81:127–35. 2016;115:140–5. doi:10.1016/j.sse.2015.08.010. doi:10.1016/j.microrel.2017.12.027. [16] Nagumo T, Takeuchi K, Yokogawa S, Imai K, Hayashi Y. New analysis [8] Toro-Frias A, Martin-Lloret P, Martin-Martinez J, Castro-Lopez R, Roca methods for comprehensive understanding of Random Telegraph Noise. E, Rodriguez R, et al. Reliability simulation for analog ICs: Goals, 2009 IEEE Int Electron Devices Meet 2009:1–4. solutions, and challenges. Integr VLSI J 2016;55:341–8. doi:10.1109/IEDM.2009.5424230. doi:10.1016/j.vlsi.2016.05.002.