This is the accepted version of the article: Maestro Izquierdo, Marcos; Martin Martinez, Javier; Crespo-Yepes, Albert; [et al.]. «Experimental verification of memristor-based material implication NAND operation». IEEE Transactions on Emerging Topics in Computing, Vol. 7, issue 4 (Oct.-Dec. 2019), p. 545-552. DOI 10.1109/TETC.2017.2760929 This version is available at https://ddd.uab.cat/record/249152 under the terms of the license IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID 1 Experimental verification of memristor-based material implication NAND operation M. Maestro, J. Martin-Martinez, A. Crespo-Yepes, M. Escudero, R. Rodriguez, M. Nafria, X. Aymerich and A. Rubio Abstract— Memristors are being considered as promising devices for highly dense memory systems as well as the potential basis of new computational paradigms. In this scenario, and in relation with data processing, one of the more specific and differential logic functions is the material implication logic also named as IMPLY logic. Many papers have been published in this framework but few of them are related with experimental works using real memristor devices. In the paper authors show the verification of the IMPLY function by using Ni/HfO2/Si manufactured devices and laboratory measurements. The proper behavior of the IMPLY structure (2 memristors) has been shown. The paper also verifies the proper operation of a two-steps IMPLY- based NAND gate implementation, showing the electrical behavior of the circuit in a cycling operation. A new procedure to implement a NAND gate that requires only one step is experimentally shown as well. Index Terms— IMPLY function, material implication, memristive circuits, memristors, NAND gate implementation, resistive switching. ——————————  —————————— I. INTRODUCTION M emristors, firstly introduced in 1971 by L. Chua [1] and later revisited by the research group of S. Wil- some design requirements to support the IMPLY logic family are described. However, these and most of the liams from HP Labs in 2008 [2], present very advanta- works presented in the literature are only based on simu- geous characteristics such as fast operation, high scalabil- lations and a lack of experimental works related to mate- ity and low power consumption [3]–[11] as well as non- rial implication logic implemented with real devices is volatility. These features have attracted the interest of the observed. Between the very few experimental works pre- scientific community to study memristors as potential sented in the literature, in [26] a study of material impli- candidates to implement complex memory blocks [3], cation-based gates is done, but using SiOx-based memris- [11], neuromorphic systems [12], [13], analog and digital tors and it is only focused on the IMPLY gate. Therefore, processing circuits [14]–[19] and in-memory computation experimental works to finally demonstrate the functional- systems [20], [21]. In this sense, one of the most innova- ity of the material implication-based logic circuits and to tive and interesting applications of memristors is data verify the promising results expected from simulations computing. Memristors introduce new paradigms to are still needed. Thus, in this paper, a deeper experi- implement logic computing, not based on the traditional mental investigation to contribute to the final validation Von Neumann architecture where the data are separately of the use of material implication as a new paradigm of stored in memory and processed in a processor, but over- computing architecture is performed. lapping them in the same structure [21], [22]. In this Usage of memristors in IMPLY gates can be shown sense, memristor-based material implication (IMPLY) thanks to the Resistive Switching (RS) phenomenon logic gate was proposed in [14] as a ‘stateful’ logic where which takes place in Metal-Insulator-Semiconductor or the data can be processed and stored in the same element. Metal-Insulator-Metal (MIS/MIM) structures and consists Several works have explored the use of material implica- in successive changes between two different resistance tion for logic applications. In [23], several strategies for states of the dielectric named Low Resistance State (LRS) arithmetic operations with memristors-based structures and High Resistance State (HRS), showing a memristive are described and the design of an adder and a multiplier behavior. Unipolar resistive switching in MIS memristors is presented. In [24] the authors also examine the use of can be described by thermochemical processes [27]. First memristors to design different types of adders. In [25], a change from HRS to LRS is possible due to the growth of design methodology of the IMPLY logic family, including a conductive filament along the insulator region, connect- ———————————————— ing top electrode and bottom electrode. Filament for- mation is governed by the temperature and field-induced  M. Maestro, J. Martin-Martinez, A. Crespo-Yepes, R. Rodriguez, M. Nafria, X. Aymerich are with the Departament d’Enginyeria Electrònica, generation of defects [28]. On the contrary, in LRS-HRS Universitat Autònoma de Barcelona, Bellaterra 08193, Spain change, the previously formed filament is partially de- (e-mail: marcos.maestro@uab.es, , Javier.martin.martinez@uab.es, stroyed limiting the conduction between the top electrode albert.crespo@uab.es, rosana.rodriguez@uab.es, montse.nafria@uab.es, xavier.aymerich@uab.es) and the bottom electrode. This process is controlled by  M. Escudero and A. Rubio are the Electronic Engineering Department, thermally enhanced diffusion of top electrode atoms in- Universitat Politecnica de Catalunya, Barcelona, 08034, Spain (e-mail: duced by local joule heating [28]. The HRS and LRS states manuel.escuredo@upc.edu, antonio.rubio@upc.edu). can be related with the two Boolean values implicated in xxxx-xxxx/0x/$xx.00 © 200x IEEE Published by the IEEE Computer Society 2 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID digital operations, ‘0’ and ‘1’, allowing the implementa- tion of logic gates with memristors in which material implication is based [26]. Section II describes the composition of the experi- mental devices employed in the work and we revisit the principles of the IMPLY function [14]. In section III, the IMPLY and NAND logic gates with memristors [29] are experimentally demonstrated on fabricated MIS- memristors. Moreover, in section IV a new procedure to perform the NAND logic operation is proposed, which reduces the number of sequential steps from 2 [14] to 1 as proposed in previous works [20]. Other memristor-based Fig. 2. Typical I-V characteristic of the memristors used in this work. NAND implementations can be found in the literature Voltage polarity to provoke Set and Reset processes is negative. but with more complex architectures [30] or with more than 2 steps operation procedure [19]. The procedure to mechanisms, which are of the order of pJ and µJ, respec- improve NAND gate implementation can be extended to tively, can be found in [34]. On the other hand, the stabil- perform other logic gates, with the subsequent saving of ity and variability of these samples has been previously the computing time. Finally, section V concludes with a presented in [32], [33]. Cycle-to-cycle variability, in volt- summary of the main results. ages and currents, seems to be important, although, not so relevant for the gate functionality. Despite the fact that II. MEMRISTORS DESCRIPTION the goal of this paper is not the study of variability impli- Fabricated memristors used in this work are Ni/HfO2/Si cations, device-to-device variability has been also ob- MIS devices based on (100) n-type CZ silicon wafers with served to decrease gate operation success percentages. To resistivity between 0.007Ωcm and 0.013Ωcm [31]. After perform all the measurements presented in this work, 15 standard wafer cleaning, a wet thermal oxidation process samples were used. was done at 1100ºC leading to a 200nm-thick SiO2 layer. In the memristor samples employed in this work, ini- This field oxide was patterned by photolithography and tially, approximately 20 cycles changing successively wet etching. Prior to the high-k deposition, a cleaning in between LRS and HRS were performed on each memris- H2O2/H2SO4 and a dip in Hf(5%) were performed. Subse- tor, in order to achieve a stable behavior of the conductive quently, 20nm-thick HfO2 layers were grown by atomic filament generation/destruction. After this previous layer deposition (ALD) using Tetrakis (dimethylamido)- forming process, successive changes between the HRS hafnium (TDMAH) and H2O as precursors, and N2 as and LRS in the cell can be performed with set and reset carrier and purge gas. The deposition temperature was voltages and currents in a reduced range of values. When 225ºC. The top metal electrode, consisting of a memristor is at HRS (see Fig. 2), there is a low current 200nm-thick Ni layer, was deposited by magnetron sput- flow, IOFF, due to the fact that the conductive filament is tering. The resulting structures are square cells of 5x5μm2. partially broken and, digitally, this state is associated to a A schematic cross-section of the final device structure is ‘0’ Boolean value. On the contrary, when memristor is at shown in Fig. 1. LRS (Fig. 2) a significant current flow, ION, is allowed In Fig. 2, typical I-V characteristic of a memristor is through the conductive filament. In this case, this state is depicted. Voltages at which samples change from HRS to associated to the Boolean value ‘1’. In this work, instead LRS (VSET) and from LRS to HRS (VRESET) and current at of evaluating the memristor resistance, we have consid- LRS (ILRS, ION) and at HRS (IHRS, IOFF) are also indicated. In ered the values of IOFF and ION currents (measured these samples, which present both bipolar and unipolar at -0.8V) as a measure of the ‘0’ and ‘1’ logic states, re- behavior, the unipolar type with negative voltage polarity spectively, for an easier understanding of the experi- to trigger set and reset processes gives the best endurance mental results. Therefore, the maximum value of memris- results of the RS phenomenon [32], [33]. More than 3000 tor current to be considered as ‘0’ has been stablished at cycles of negative switching can be reached [32]. During 0.1µA, whereas the minimum value achievable for the SET process, current was limited to 250µA to guarantee current to be ‘1’ state has been 10µA. good functionality of the memristor. An analysis of the energies involved in the triggering of the set and reset III. MEMRISTORS-BASED LOGIC GATES DESCRIPTION Fig. 3 (a) schematically shows an IMPLY gate, where two memristors (P and Q) have their bottom electrodes con- nected to a resistance (RG), which has the other terminal grounded. Top electrodes of memristors are used to ap- ply operational voltages, VCOND and VIMPLY (in the litera- ture this voltage is labeled as VSET, however to avoid misunderstanding with VSET in Fig. 2, VIMPLY is considered Fig. 1. Cross-section of the memristor device used in this work. instead), in order to implement the IMPLY truth table AUTHOR ET AL.: TITLE 3 nected (2 SMUs for IMPLY case and 3 for NAND case). Additionally, a voltage source unit (VMU) was connected to monitor the voltage VG. For the initialization step, volt- age ramps were separately applied to every memristor to switch memristors to ‘0’ or ‘1’ state according to the case. Then, to perform the operation step, constant voltages were simultaneously applied to the memristors involved in such a step. After several attempts, trying different voltages values, finally the chosen operation voltages have been VCOND = -2V and VIMPLY = -4V, which are the ones that produce the better IMPLY gate performance in most of the analyzed gate cases. Eventually, the final states of memristors were measured applying a small voltage ramp up to -0.8V. B. IMPLY logic gate For the IMPLY experimental measurements using the circuit shown in Fig. 3(a), one of the cases from 1 to 4 of the truth table (Fig. 3(c)) is selected. Memristors P and Q Fig. 3. (a) IMPLY and (b) NAND gates schematic circuits. (c) IMPLY are initialized to those states corresponding to the select- and (d) NAND gates truth tables ed case, that is ‘0’ (memristor at HRS) or ‘1’ (memristor at LRS). Operation voltages (VP and VQ) are applied to shown in Fig. 3(c). The gate operates as ‘P implies Q’ or ‘if change the initial Q state (for case 1) or to keep it for the P then Q’, being the state of Q the output of the gate. The rest of the cases. Operational voltages applied to memris- possible combinations of the initial logic states of memris- tors do not depend on the considered case. For our devic- tors P and Q result in four different cases, as it is indicat- es, the voltage applied to P is VP = VCOND = -2V and ed in the table. In case 1, for example, both memristors VQ = VIMPLY = -4V to Q. Currents through P and Q and the must be initially at HRS, i.e. ‘0’ logic state, then, when the voltage, VG, are now measured to verify the memristors proper voltage values are applied to the memristors, Q states, both before and after the voltage application. state changes to LRS because the voltage drop across it is Fig. 4 shows states of the memristors for the four IM- enough to provoke such resistance change. On the contra- PLY cases (from top to bottom, case 1 to case 4). The states ry, the state of P remains unaltered keeping ‘0’ logic state of P and Q before (initial states) and after (final states) since its voltage drop is below the voltage necessary to operation are shown expressed in terms of the current originate a resistance state change. For the rest of the flowing through the devices (equivalent to the devices’ cases, no state change is provoked in any of the memris- resistances). We can observe that the truth table is accom- tors. Applying the same operational voltage values as in plished correctly. case 1, initial logic states are kept accomplishing the truth table in Fig. 3(c). A detailed circuital analysis of the IM- PLY gate can be found in [15]. CASE 1: The IMPLY gate can be the basis to implement other logic gates. Fig. 3(b) shows the schematics of a NAND gate. The structure is similar to the IMPLY gate but, in this case, a third memristor (S), biased with VS, is added CASE 2: to P and Q of the IMPLY gate as indicated in the Fig. 3(b) [25]. The output of the NAND cell is stored in the state of memristor S. The truth table of the NAND gate is indicat- ed in Fig. 3(d). Note that RG value has been 1MΩ, in order to accomplish the relation RONVCOND1, (2) would be obtained (substituting these functionality of the NAND are againVCOND1 = -2V, VCOND2 = values in (1) and simplifying). Considering the resistance 0V and VIMPLY = -4V. For the measurement of final states of relation described in the last paragraph, VG would be memristor a voltage ramp up to -0.8V has been applied. negligible. Fig. 8 graphically shows the proposed sequence to per- RGVIMPLY  2 RGVCOND1 form the NAND gate in only one operation step. Firstly, all VG  0 (2) memristors are initialized (initial states). Later, the unique Roff  3RG operation step takes place applying the adequate voltages to P, Q and S memristor simultaneously according to the case. Then, since VG≈0, voltage drops across P and Q would The voltage selection was controlled by programming the be approximately VCOND1, and across S almost VIMPLY. This proper voltages to the terminals for each logic case. Finally, would provoke the S resistance change from ROFF (‘0’) to the memristors state is read to verify the correct gate behav- RON (‘1’), while P and Q remain the same state (‘0’) with ior. The initialization and evaluation of memristors states is resistance ROFF. also done when the standard NAND procedure is used. In case 2, resistances of memristors P, Q and S should However, the number of operation steps performed to pro- be ROFF, RON and ROFF respectively and, as before, S re- voke the NAND gate output is different: with the standard sistance should change to RON. If P and Q were biased at procedure two operation steps are required (first an IMPLY VCOND2 and S with VIMPLY; VG would be given by (3). Tak- operation between P and S memristors and, secondly, an- ing into account the memristor resistance values, VG other IMPLY operation between Q and S memristor). With would be negligible again. The voltage drops through P, this new NAND operation, only one operation step, where Q and S would be VCOND2, VCOND2 and VIMPLY respectively the three memristors are involved at the same time, is done, (with VIMPLY > VCOND2) provoking the change of the S re- instead of the two operation steps of the standard procedure. sistance from ROFF to RON and modifying the stored logic Table I shows the combination of the operation voltages, state from ‘0’ to ‘1’. As expected, P and Q would remain which are applied simultaneously and verify the required in the same initial state. relationships. This provokes an S-output that corresponds to RG RonVIMPLY  ( RG Ron  RG Roff )VCOND 2 the NAND truth table. VG   0 (3) TABLE I ( Roff  2 RG ) Ron  RG Roff EXPERIMENTAL VOLTAGES APPLIED SIMULTANEOUSLY TO THE NAND CIRCUIT TO PROVOKE THE DIFFERENT CASES OF THE NAND OUTPUT IN Similarly occurs in case 3. Since P and Q are supposed ONLY ONE OPERATION STEP. to be interchangeable and initial states are RP=RON, CASE VP (V) VQ (V) VS (V) RQ=ROFF and RS=ROFF, VG follows the same equation, (3). 1 ‐2 ‐2 ‐4 Therefore, voltage drops across memristors, considering 2 0 0 ‐4 VP = VQ = VCOND2 and VS= VIMPLY, would be the same as in 3 0 0 ‐4 case 2 giving the correct final memristors states. 4 ‐2 ‐2 ‐4 Finally, in case 4, initial states of memristors P, Q and S are equal to RON, RON and ROFF, respectively and S re- sistance should not change. If voltages applied to P and Q were VCOND1 and VS = VIMPLY, VG would be given by the expression in (4). RG RonVIMPLY  2 RG Roff VCOND1 VG   VCOND1 (4) ( Roff  RG ) Ron  2 RG Roff Fig. 8. Schematic flow sequence of one operation step procedure for NAND logic gate. 6 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID The experimental results obtained following previous be addressed in future works. procedure are presented in Fig. 9, where initial and final memristor states are depicted for all NAND cases. Interme- VI. CONCLUSIONS diate states (shown when two sequential steps were re- In this paper, memristor-based IMPLY and NAND quired, Fig. 6) do not appear because in this case, only one logic gates have been experimentally demonstrated operation step is needed. These results demonstrate that memristor-based NAND operation is possible using unique- using Ni/HfO2/Si manufactured devices. Successive ly one step. Successive operations were also performed to NAND operations (for all four input cases) have been obtain randomly, on the same gate, the different logic cases also successfully performed, showing the operation of the NAND gate, with only one operation step. correctness even in the presence of the inherent cycle- Fig. 10 shows initial and final memristors states for all to-cycle device fluctuations. Additionally, a new pro- NAND cases in a successive operation measurement. As in cedure to operate the NAND gate has been proposed, two-step NAND (Fig. 7) several ‘0’ states are in the forbid- which requires only one step, reducing the computing den region (current reaching values of 1µA). However, since current values at ‘1’ are mostly above 10µA, the successive time when compared to previous IMPLY-based im- performance of one-step NAND has been also performed. plementations (that requires two steps). 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Hamdioui, “Fast boolean logic mapped on memristor cross- bar,” in 2015 33rd IEEE International Conference on Computer Marcos Maestro-Izquierdo, graduated with a Design (ICCD), 2015, pp. 335–342. degree in physics from Universidad de Salamanca [19] G. Snider, “Computing with hysteretic resistor crossbars,” in 2009. He obtained the master's degrees in Appl. Phys. A, vol. 80, no. 6, pp. 1165–1172, Mar. 2005. physics instrumentation from Universidad de Valladolidand and in micro and nanoelectronic [20] S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, “Pinatubo: A from Universitat Autònoma de Barcelona in 2012 processing-in-memory architecture for bulk bitwise opeartions and 2013, respectively. Currently, he is working in in emerging non-volatile memories,” in Proceedings of the 53rd the group of 'Reliability of Electron Devices and Annual Design Automation Conference on - DAC ’16, 2016, pp. Circuits' (REDEC) within Electronics Engineering 1–6. Department of the UAB to obtain his Ph.D. de- gree. His research interests are focused on the study of Resistive [21] S. Hamdioui et al., “Memristor for computing: Myth or reali- switching phenomenon and its applications in diverse fields ty?,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, pp. 722–731. Javier Martin-Martinez, born in Barcelona, he [22] E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, and R. Waser, was graduated in Physics in 2004 for Universi- “Beyond von Neumann—logic operations in passive crossbar ty of Zaragoza (UZ). He has colaborated with arrays alongside memory operations,” Nanotechnology, vol. 23, the Electronic Department of Universidad de Zaragoza investigating algorithms of learning no. 30, p. 305205, Aug. 2012. for neu-ronal networks. At the moment, he is a [23] K. Bickerstaff and E. E. Swartzlander, “Memristor-based arith- FPI grant holder in Universitat Autònoma de metic,” in Conference Record of the Forty Fourth Asilomar Barcelona (UAB), where his research is focused on the dielectric Conference on Signals, Systems and Computers, 2010, pp. 1173– breakdown and degradation impact in transistors and circuits. Re- 1177. cently, he has done a stay in the University of Padova where he has studied the dielectric degradation in CMOS technologies [24] D. Mahajan, M. Musaddiq, and E. E. Swartzlander, “Memristor based adders,” in 48th Asilomar Conference on Signals, Sys- Albert Crespo Yepes received the degree in tems and Computers, 2014, pp. 1256–1260. Telecomunications Engineering in 2008. In 2012 he finalized his Ph. D. studies in Electron- [25] S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, ic Engineering for UAB (Universitat Autònoma and U. C. Weiser, “Memristor-Based Material Implication (IM- de Barcelona). Currently, he is post-Ph.D. PLY) Logic: Design Principles and Methodologies,” IEEE Trans. researcher teaches in this university. His work Very Large Scale Integr. Syst., vol. 22, no. 10, pp. 2054–2066, is focused on electron device characterization Oct. 2014. and the study of the reliability and the aging mechanisms such as Dielectric Breakdown, [26] F. Zhou, L. Guckert, Y.-F. Chang, E. E. Swartzlander, and J. Lee, CHC and BTI. He has also widely studied the Resistive Switching “Bidirectional voltage biased implication operations using SiOx phenomenon for applications in the field of non-volatile memories. based unipolar memristors,” Appl. Phys. Lett., vol. 107, no. 18, Other contributions are focused on the characterization of emerging p. 183501, 2015. devices and technologies, such as Ink printed devices, for low-cost and low-power applications in IoT, sensing or Instrumentation. 8 IEEE TRANSACTIONS ON JOURNAL NAME, MANUSCRIPT ID Manel Escudero No biography. Rosana Rodríguez received the Ph. D. in Elec- trical Engineering from Universitat Autonoma de Barcelona (UAB) in 2000. Funded by the Ful- bright program, she worked on devices and circuits reliability at the IBM Thomas J. Watson Research Center (USA). Currently, she is asso- ciate professor at the Universitat Autonoma de Barcelona. Her main research interests are focused on the electrical characterization and reliability of CMOS devices. In particular, she analyses the effect of CMOS failures such as dielectric breakdown, BTI and Channel Hot Carriers on the performance of devices and digital and analogical circuits, as well as the process/time-related variability. Her current research topics also include the study of the resistive switching phenomenon and its applications. Montserrat Nafría received the Ph.D. degree in Physics from the Universitat Autonoma de Bar- celona, Spain, in 1993, where she is currently a Full Professor at the Department of Electronic Engineering. Her major research interests in- clude CMOS device and circuit reliability. Cur- rently, she is working on the characterization and modelling of the aging (BTI and channel hot carrier degradations) and variability of advanced MOS devices. This is done from the nanoscale level, by studying the phenomena using Atomic Force Microscope-related techniques, up to circuit level, by developing models for circuit simulators that account for the time- dependent variability of the devices. She is also interested in the characterization and modelling of Resistive RAM and graphene- based devices. She is the author or coauthor of more than 250 research papers in scientific journals and conferences in all these fields. ORCID ID: 0000-0002-9549-2890. Xavier Aymerich was graduated in Physics in 1975 and obtained the Ph.D. in 1980 from Universitat Autònoma de Barcelona, with a thesis on tunnel electronic devices performed in collaboration with the LAAS in Toulouse. Full Professor from 1991 in the Dept of Physics at UAB, and from 1996 member of the Depart- ment of Electronic Engineering. His scientific interest lies in field of the reliability of micro and nanoelectronic devices, including ultra thin gate oxides, high-k dielectrics, NBTI, resistive switching, ad- hoc reliability characteriza- tion of devices by combining SPM tools and conventional microelec- tronic techniques. Also he is interested in the approach to the relia- bility at circuit level, including effects on devices variability and circuit reliability simulation. He is member of several national and interna- tional committees and authored more than 350 research papers in scientific journals and conferences. Antonio Rubio (M.S.’77, Ph.D’82) has been As- sociate Professor of the Electronic Engineering Department at the Industrial Engineering Faculty (UPC) and Professor of the Physics Department at the Balearic Islands University. He is currently Professor of Electronic Technology at the Tele- communication Engineering Faculty in the Poly- technical University of Catalonia, UPC, Barcelo- naTech. His research interests include VLSI design and test, device reliability, Fault Tolerant systems, new emerging devices and circuits and high speed circuit design.