This is the submitted version of the article: Li F., Mawby P., Song Q., Perez-Tomas A., Shah V., Sharma Y., Hamilton D., Fisher C., Gammon P., Jennings M.. A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability. IEEE Transactions on Electron Devices, (2020). 67. 8935512: 237 - . 10.1109/TED.2019.2954911. Available at: https://dx.doi.org/10.1109/TED.2019.2954911 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 A first evaluation of thick oxide 3C-SiC MOS capacitors reliability Fan Li, Qiu Song, Amador Perez-Tomas, Vishal Shah, Yogesh Sharma, Dean Hamilton, Craig Fisher, Peter Gammon, Mike Jennings, and Phil Mawby  electronics systems can reach up to 30 years [1], thus gate Abstract— Despite the recent advances in 3C-SiC technology, dielectrics are expected to have a similar lifetime. In the early there is a lack of statistical analysis on the reliability of SiO2 layers days of the Si industry, the SiO2 on Si system was intensively on 3C-SiC, which is crucial in power MOS device developments. studied and is now well developed compared with This paper presents a comprehensive study of the medium and investigations performed on 4H-SiC [2-12]. Even now, the gate long-term time-dependent dielectric breakdown (TDDB) of 65 nm thick SiO2 layers thermally grown on a state-of-the-art 3C-SiC/Si oxide reliability of large active 4H-SiC MOS devices (5-50 wafer. Fowler-Nordheim (F-N) tunnelling is observed above 7 mm2) is still not as good as the early Si devices with comparable MV/cm and an effective barrier height of 3.7 eV is obtained, which gate oxide area [13]. Regardless, in the last decade, a great is highest known for native SiO2 layers grown on the improvement of the lifetime of SiO2 on 4H-SiC has been seen, semiconductor substrate. The observed dependence of the oxide from below 1000 s (6 MV/cm, 350 °C) [3] to most recently reliability on the gate active area suggests the oxide quality has not 2300 h (6 MV/cm, 250 °C) [6]. Yet it was believed impossible reached the intrinsic level. Three failure mechanisms were identified, confirmed by both medium and long-term results. to reach the stability of the Si/SiO2 interface, due to an inherent Whereas two of them are likely due to extrinsic defects from smaller conduction bands offset ∆EC between 4H-SiC and SiO2 material quality and fabrication steps, the one dominating the high [4]. In the high field condition, the oxide intrinsic degradation field (>8.5 MV/cm) should be attributed to the electron impact is believed to be dominated by F-N tunnelling [14], and the ionization within SiO2. At room temperature, the field acceleration affinity difference at the semiconductor/oxide interface is the factor is found to be ≈0.906 dec/ (MV/cm) for high fields, and the potential barrier ΦB for such tunnelling. In a strong inversion projected life-time exceeds 10 years at 4.5 MV/cm. case such as the MOSFET being switched on, ΦB≈∆EC [4]. The Index Terms— Reliability, 3C-SiC, MOS capacitor, TDDB, theoretical value of ∆EC for 4H-SiC/SiO2 is 2.7 eV and had failure mechanism. recently been experimentally reported [15], whereas the value for Si is 3.2 eV, and for 3C-SiC 3.7 eV [16], potentially the most stable among the three. Moreover, the smaller bandgap means I. INTRODUCTION most of the traps troubling the 4H-SiC/SiO2 interface are S ILICON CARBIDE (SiC) can provide better electrical located in the conduction band of 3C-SiC, namely not performance than Si in more harsh operation conditions contributing to degrade the channel mobility, thus lower (high power, high frequency and high temperature), thus have channel resistance for a MOSFET. 3C-SiC technology is not yet been considered as the next generation substrates for power as popular as 4H-SiC, mainly due to the lack of device grade, devices. 4H-SiC Schottky barrier diodes (SBD), JFETs, and high quality 3C-SiC substrates. However, the ability to deposit MOSFETs are commercially available now. The 4H-SiC SBDs 3C-SiC on large area Si wafers (6-inch 3C-SiC on Si wafers proved to be a success in boost converters, whereas the switches demonstrated 20 years ago [17]) makes it attractive in terms of (JFETs or MOSFETs) have not been widely accepted as their cost-effective. In the last ten years, there have been many Si counterparts. improvements in 3C-SiC substrate preparation [18-24] that a Compared with other wide band gap (WBG) semiconductors, defect density below 400 cm-1 became possible [24]. There SiC has the advantage that SiO2 layers can be directly thermally were also further developments in 3C-SiC device processing, grown on the epilayer as the gate dielectric for MOS devices. including implantation [25, 26], oxidation [27-29], and The reliability of this SiO2 layer is a major attribute of a metallisation [30, 31]. 600 V vertical power MOSFET was MOSFET development and the required lifetime of power demonstrated with a specific on-resistance of 8.2 mΩ.cm2 [32]. This paragraph of the first footnote will contain the date on which you Y. K. Sharma is with Dynex Semiconductor Ltd, Doddington Rd, Lincoln submitted your paper for review. This work was part of the Challenge project, LN6 3LF, UK. founded by European Commission, ID 720827. D.P. Hamilton is with Institute of Engineering Sciences, De Montfort F. Li, Q. Song, C.A. Fisher, V.A. Shah, P.M. Gammon, and P.A. Mawby are University, Leicester, LE1 9BH, UK. with the School of Engineering, University of Warwick, Coventry, CV4 7AL, M.R. Jennings is with College of Engineering, Swansea University, UK. (e-mail: f.li.3@ warwick.ac.uk). Swansea, SA1 8EN, UK. A. Perez-Tomas is with Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and The Barcelona Institute of Science and Technology, Campus UAB, Bellaterra, 08193 Barcelona, Spain. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 Regarding the 3C-SiC/SiO2 interface, some study was dielectric. Photo lithography and reactive ion etching (RIE) was performed on the interface trap density [33, 34] and channel used to selectively etch the deposited 2 µm SiO2 down to the mobility [29, 35, 36], whereas very little on the reliability. In 3C-SiC surface, where the gate thermal oxidation occurred. Dry [16], dielectric breakdown of very thin (6-7 nm) and small area oxidation (1200 ºC, 10 mins, 1 slm O2) followed by a post (100 nm diameter) thermally grown SiO2 on 3C-SiC(111) was oxidation anneal in N2O (1200 ºC, 120 mins, 1 slm N2O) was studied by Time Dependent Dielectric Breakdown (TDDB) test performed to obtain the gate oxide. The final gate oxide was at 10 V (≈15 MV/cm), and Weibull slope β values of 4.4-5.1 around 65 nm thick, measured by the ellipsometry. In our were obtained. This is close to the performance of SiO2 layers previous investigations, no significant degradation in the 3C- on Si with similar thickness. However, for thin oxides the SiC surface roughness was observed following AFM leakage current stays almost constant until failure, which is in evaluations after post implantation anneal [26] and thermal contrast to thick oxides, where electron/hole trapping cause the oxidation [27]. Ohmic metallisation was obtained by RIE current level to change a lot during stress [14]. Since the etching the passivation oxide and evaporating first a 30 nm Ti tunnelling current generates defects in the oxide, leading to layer, followed by a 100 nm Ni layer on the N+ regions. A rapid their eventual degradation [4], thin and thick SiO2 layers tend thermal anneal at 1000 ºC for 2 mins in Ar was performed to to have different failure mechanisms. Also, under the same form the ohmic contact with specific contact resistance below electric field, carriers in thicker oxides are more likely to gain a 1×10-5 Ω.cm2 [31]. Finally, the gate contact was defined by higher energy for impact ionization [9], which is often selectively evaporating 500 nm thick Al above the gate oxide considered as another potential cause of oxide failure. Practical region. The final device has a circular gate active area, and a power devices usually have thick (>50 nm) SiO2 layer in order cross section view of the structure is shown in Fig. 1. MOS to sustain the gate voltage [4, 7]. To the best of our knowledge, capacitors with three gate diameters were fabricated, namely the reliability of thick SiO2 on 3C-SiC has not been reported. Φ100 µm, Φ200 µm and Φ400 µm. In this paper, 3C-SiC MOS capacitors were fabricated with ≈65 nm thermally grown SiO2 layers as the gate dielectric. I-V characterisation was used to study the effective barrier height at the 3C-SiC/SiO2 interface. Medium-term test lasting weeks was then performed and the failure distribution was obtained for a wide electric field range of 4.5-10.5 MV/cm. Following the medium-term results, long-term TDDB tests lasting months were conducted for 6, 7.5, 8.5 and 9 MV/cm. All characterisations were performed at room temperature. Based on the failure distribution and TDDB plots, Weibull models were used to predict the fabricated MOS capacitors failure rate and lifetime. II. EXPERIMENTAL 10 µm thick unintentionally doped (<1×1016 cm-3) N-type Fig. 1. A schematic cross section view of the fabricated circular lateral 3C- SiC MOS capacitors, dimensions are not to scale. 3C-SiC(100) layers were epitaxy grown on-axis from a 4-inch Si(100) substrate. The as-grown 3C-SiC epilayer was treated with a chemical mechanical polishing (CMP) step in order to III. RESULTS AND DISCUSSIONS obtain a low surface root mean square roughness ≈0.2 nm, A. Capacitance-voltage (C-V) characterisation measured by atomic force microscopy (AFM). Since it is the Room temperature C-V (1 kHz and 1 MHz) characterisations 3C-SiC/SiO2 interface that is of interests here, lateral MOS were performed on these MOS capacitors using a LCR meter. capacitors were fabricated in order to minimize the disturbing A negative flat band voltage was observed as shown in Fig. 2, electrical effects from the 3C-SiC/Si heterojunction. For ohmic which is also commonly reported in the literature [32, 36, 37]. contact, nitrogen was selectively implanted to form a 300 nm It is generally believed to be caused by the nature of donor-like deep box profile with the peak concentration of ≈5×1020 cm-3, states at the 3C-SiC/SiO2 interface, which have a lower density and a post implantation anneal was performed at 1350 ºC for 2 than 4H-SiC but are positively charged [38]. The effective fixed hours in Ar atmosphere. No surface capping layer was used charge density was calculated to be around 2.1×1012 cm-2 during the post implantation anneal. Our previously study [26] according to the flat band shift from the ideal value. This value shows that, this will lead to a ≈15% activation of the implanted is typical among lately reported results [16, 28]. Using the high- nitrogen dopants. After the post implantation anneal, solvent low method [39], the interface trap density at 0.2 eV from the cleans were performed (acetone, propanol, acetone, and 3C-SiC conduction band edge was extracted to be 2.5×1011 cm- methanol, each step 5 mins) in an ultrasonic bath. Following 2 eV-1, which is among the lowest values reported in recent that, a two-stage acid clean was applied, first piranha literatures [28, 34, 40]. (H2SO4:H2O2=3:1, 15 mins) then RCA (RCA1 15 mins+ RCA2 15 mins). A 2 µm thick SiO2 layer was deposited via low pressure chemical vapour deposition as the surface passivation > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 theoretical value of 3.7 eV. C. Medium-term reliability and failure distribution We investigated the failure distribution of these MOS capacitors in a wide field range of 4.5-10.5 MV/cm. For each studied electric field, the gate bias VG was kept constant for 1 hour before increasing to the next value. More details about this method can be found in [1]. Fig. 2. Experimental (1 MHz) and ideal C-V characterisations of the fabricated lateral MOS-C. Fig. 4. The failure distribution of Φ100, Φ200 and Φ400 MOS capacitors in the electric field range of 4.5-10.5 MV/cm. For each gate diameter, 80 MOS capacitors were tested. As can be seen in Fig. 4, the failure distribution varies considerably with the gate diameter that, larger devices tend to fail more easily than smaller ones as the gate bias elevates. Similar area dependence was observed also in 4H-SiC TDDB results (area of 100×100-200×800 µm2) [7]. At least three mechanisms are Fig. 3. Representative gate leakage current densities as a function of the electric field in the oxide for the Φ100 MOS capacitors. recognisable from the failure distribution of the Φ100 MOS capacitors. Neglecting the 3 premature failures at 4.5 MV/cm, B. Dielectric breakdown and F-N tunnelling it can be seen that between 6 MV/cm and 7.5 MV/cm, the By performing room temperature I-V measurements using a number of failures accumulate gradually. In this low field Keysight B1500 parameter analyser, the leakage current density range, failure is crucially determined by the number of extrinsic of Φ100 devices as a function of the electric field in the oxide defects per device (namely gate active area) and defined as is obtained and shown in Fig. 3. As can be seen in Fig. 3, when mechanism I. From the literature, these first priority defects the electric field reaches ≈7 MV/cm, the gate leakage current may be pre-existing basal plane dislocations in the 3C-SiC density becomes dominated by F-N tunnelling, which usually epilayer [42], or local step-bunching edges where dielectric comes into effect at a lower electric field of 5-5.5 MV/cm for break down can be accelerated [16]. Reaching 7.5 MV/cm, it 4H-SiC MOS gate oxides [7-12, 15]. The effective barrier seems that almost all mechanism I failures have occurred, and height ΦB can be obtained by fitting the linear region of the the increase of total failure number slows down, suggesting a experimental “ln(J/Eox2) vs 1/Eox” plot to the following new mechanism II becoming dominant. Mechanism II induced expression [15]: failures have a much smaller increase rate against elevating electric fields (more obviously shown later in Fig. 5), thus can be easily overshadowed by other mechanisms. The cause of ( ) mechanism II could be the extrinsic defects created during the ln = − (1) device fabrication or a relatively high stacking fault density in the 3C-SiC epilayer. Above 8.5 MV/cm, a considerably sharp where J is the gate leakage current density, Eox is the electric increase of the total failed devices is observed, namely field within the gate oxide, m0 is the free electron mass, mechanism III. It is worth mentioning that 8.5-9 MV/cm is also mox=0.42m0 [41] is the effective electron mass, q is the unit previously reported in 4H-SiC TDDB tests as a juncture point electron charge, and h is the Plank constant. The experimental where the failure mechanism changes [7-9]. For 4H-SiC, one of effective barrier height ΦB was obtained as 3.65-3.71 eV for the the common explanations for such change at high electric fields representative results shown in Fig. 3, approaching the is F-N tunnelling. As mentioned previously, F-N tunnelling > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 almost always occurred around 5-5.5 MV/cm in the case of 4H- indicating a great room for further improvements if mechanism SiC, and here we have shown that it is delayed to above 7 I can be minimized by improving material quality. MV/cm for 3C-SiC. The fact they both change failure D. TDDB mechanisms around 8.5 MV/cm makes the F-N tunnelling explanation not satisfactory. On the other hand, the electron Long-term TDDB test was performed on Φ100 MOS impact ionization within the SiO2 is determined by the oxide capacitors at room temperature using a custom-built dielectric thickness and electric field. For the mostly studied ≈50 nm thick breakdown rig. Gate leakage currents of up to 32 devices were oxides of power MOS devices, the impact ionization is monitored simultaneously in parallel, and the maximum current expected to occur at an electric field strength of ≈8 MV/cm [43, level was separately limited to 1 µA by series connected 44]. While for thin oxide layers, impact ionization occurs at resistors. Any device with a gate leakage increasing to above 1 higher electric fields, which also explains why even at a very µA was removed from operation to protect the adjacent devices. high electric field of 15 MV/cm, a Weibull distribution can still Literatures have suggested that the thick gate oxide breakdown be observed for the TDDB results of very thin (6-7 nm) SiO2 is a “weakest link” type of problem [8, 47, 48], thus can be layers on 3C-SiC [16]. As such, here we attribute mechanism described by the Weibull distribution expression as below: III to the electron impact ionization. [ ( ) ] 𝐹(𝑇 ) = 1 − 𝑒 % (3) where TBD is the TDDB running time, t63% is the characterisitc time when 63% of all tested devices fail, and β is the Weibull slope, which is an indicator of failure mechanism variance between devices and should increase with reducing number of mechanisms. Fig. 5. Weibull distributions of Φ100 MOS capacitors as a function of applied gate bias, F is the failure rate and VUSE is the normal use voltage. The three failure mechanisms can be more easily distinguished for Φ100 MOS capacitors by plotting -ln(1-F) against VG-VUSE as shown in Fig. 5. F is the failure rate and VUSE is the nominal voltage of the device. Since the normal operating electric field of MOS devices is typically 3 MV/cm [4, 8], here we assume a VUSE of 20 V. An exponential function [45] described by Eq. (2) can be used to fit the three mechanism Fig. 6. Weibull distributions of devices failures at various electric fields on regions as seen in Fig. 5. Φ100 MOS capacitors, obvious premature failures have been removed. ( ) Measurements were taken for 6 MV/cm, 7.5 MV/cm, 8.5 −ln(1 − 𝐹) = 𝑎 ∙ 𝑒 (2) MV/cm and 9 MV/cm, and the Weibull distributions are shown in Fig. 6 with obvious premature failure tails removed. Even at a and b are the fitting parameters. By multiplying a by 106, high electric fields above 8.5 MV/cm, the extracted β values are the maximum failure parts per million (PPM) of the Φ100 MOS still very low ≈1, an order of magnitude smaller than the values capacitors working for 1 hour at 3 MV/cm and room reported for 4H-SiC [7], suggesting that mechanism II may still temperature can be estimated. With the low field being be working behind the scene at such high fields. It can be seen dominated by mechanism I, the failure rate can be estimated to in Fig. 6 that, the slope β for 9 MV/cm and 8.5 MV/cm are be around 3450 PPM, which is close to the latest 4H-SiC almost the same (≈1), whereas considerably reduced to 0.39 for MOSFET results of 4100 PPM [45]. Although the 4H-SiC 7.5 MV/cm. From previous discussions, we know it is because MOSFETs were tested at a higher temperature (150 °C) and a of the change of dominating failure mechanism from II to III longer gate bias (168 h), the channel length of these commercial with elevated electric fields. Further reducing the test field to 6 MOSFETs usually goes down to 1 µm [46], namely 10-100 MV/cm confirmed an increase of β to 0.58 due to mechanism I, times smaller gate active area than the Φ100 MOS capacitors agreeing with the medium-term distribution analysis. studied here. Extrapolation from the high field (>8.5 MV/cm) To project the lifetime of the fabricated MOS capacitors, t63% data points suggests a much lower failure rate of 40 PPM, is plotted against the applied gate electric field (the E model > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 [49]) as seen in Fig. 7. The field acceleration parameter is and 9 MV/cm. The field acceleration factor is found to be extracted to be 0.906 dec/ (MV/cm) for 7.5-9 MV/cm. From the ≈0.906 dec/(MV/cm) in the studied range. Both the medium- projection, the lifetime of these devices can reach 10 years at term and long-term tests show a failure mechanism change of room temperature with a maximum operating electric field of these MOS capacitors at 8.5 MV/cm, which is most likely 4.5 MV/cm as shown in Fig. 7. Temperature has a significant caused by the impact ionization of electrons rather than the F- impact on the life time of SiO2. Although the testing rig is N tunnelling. Although the fabricated MOS capacitors are still limited to room temperature, higher temperature performance suffering from a high number of extrinsic defects and further of these MOS capacitors can still be estimated using the improvements are required, the projected lifetime is still Arrhenius model t63% ∝ exp(Ea/kT), where Ea is the thermal remarkable and can reach 10 years, at 4.5 MV/cm and room activation energy. 3C-SiC MOSFETs operating at 300 °C have temperature. been demonstrated [36], but there were no reports on the Ea value. From the Al gated 4H-SiC MOS capacitor results [50], REFERENCES 0.5 eV was assumed for these 3C-SiC devices, and the life time projection for 150 °C is shown in Fig. 7. The predicted critical [1] J. Lutz, H. Schlangenotto, U. Scheuermann, and R. De Doncker, electric field required for 10 year life time drops considerably "Reliability and Reliability Testing," in Semiconductor Power Devices: Physics, Characteristics, Reliability, 2nd ed., Springer International to 1.4 MV/cm at 150 °C, much lower than the 4H-SiC MOS Publishing AG, pp. 489-581, 2018. DOI: 10.1007/978-3-319-70917-8. capacitors results, ≈6 MV/cm [8]. However, it should be noted [2] A. K. Agarwal, S. Seshadri, and L. B. Rowland, "Temperature that, due to a positively charged 3C-SiC MOS interface as dependence of Fowler-Nordheim current in 6H- and 4H-SiC MOS capacitors," IEEE Electron Device Lett., vol. 18, no. 12, pp. 592-594, mentioned before, a forward gate bias accumulates more 1997. DOI: 10.1109/55.644081. electrons at the 3C-SiC/SiO2 interface at room temperature [3] L. A. Lipkin and J. W. Palmour, "Insulator investigation on SiC for compared with the 4H-SiC case. As such, the actual improved reliability," IEEE Trans. Electron Devices, vol. 46, no. 3, pp. temperature effects may be smaller than predicted in Fig. 7. 525-532, 1999. DOI: 10.1109/16.748872. [4] R. Singh and A. R. Hefner, "Reliability of SiC MOS devices," Solid-State Electron, vol. 48, no. 10, pp. 1717-1720, 2004/10/01/ 2004, DOI: 10.1016/j.sse.2004.05.005. [5] S. Krishnaswami, M. Das, B. Hull, S.H. Ryu, J. Scofield, A. Agarwal, and J. Palmour, "Gate oxide reliability of 4H-SiC MOS devices," in Proc. 43rd Annu. IEEE Int. Rel. Phys. Symp., 2005, pp. 592-593, DOI: 10.1109/RELPHY.2005.1493158. [6] K. Matocha and R. Beaupre, "Time-Dependent Dielectric Breakdown of Thermal Oxides on 4H-SiC," Mater. Sci. Forum, vol. 556-557, pp. 675- 678, 2007. DOI: 10.4028/www.scientific.net/MSF.556-557.675. [7] K. Matocha, G. Dunne, S. Soloviev, and R. Beaupre, "Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 1830-1834, 2008, DOI: 10.1109/TED.2008.926595. [8] M. Gurfinkel, J.C. Horst, J.S. Suehle, J.B. Bernstein, Y. Shapira, K.S. Matocha, G. Dunne, and R.A. Beaupre, "Time-Dependent Dielectric Breakdown of 4H-SiC/SiO2 MOS Capacitors," IEEE Trans. Device and Materials Reliability, vol. 8, no. 4, pp. 635-641, 2008. DOI: 10.1109/TDMR.2008.2001182. [9] L. C. Yu, G. T. Dunne, K. S. Matocha, K. P. Cheung, J. S. Suehle, and K. Sheng, "Reliability Issues of SiC MOSFETs: A Technology for High- Temperature Environments," IEEE Trans. Device and Materials Fig. 7. Time to breakdown as a function of the applied electric field of Φ100 Reliability, vol. 10, no. 4, pp. 418-426, 2010. DOI: MOS capacitors and the projection of lifetime using the E model. 10.1109/TDMR.2010.2077295. [10] T. Watanabe, S. Hino, T. Iwamatsu, S. Tomohisa, and S. Yamakawa, "Mechanism of Depletion-Mode TDDB for 4H-SiC MOS Structure," IV. SUMMARY IEEE Trans. Device and Materials Reliability, vol. 17, no. 1, pp. 163-169, A reliability study has been thoroughly performed on 3C-SiC 2017. DOI: 10.1109/TDMR.2016.2635160. [11] P. Samanta and K. C. Mandal, "Leakage current conduction, hole MOS capacitors at room temperature, including leakage current injection, and time-dependent dielectric breakdown of n-4H-SiC MOS evaluation, medium-term constant voltage and long-term capacitors during positive bias temperature stress," J. Appl. Phys, vol. TDDB tests. The effective barrier height at 3C-SiC/SiO2 is 121, no. 3, p. 034501, 2017. DOI: 10.1063/1.4973674. [12] A. Xiang, X. Xu, L. Zhang, Z. Li, J. Li, and G. Dai, "Origin of temperature experimentally obtained as very close to the theoretical value of dependent conduction of current from n-4H-SiC into silicon dioxide films 3.7 eV, and the F-N tunnelling is found to be dominating the at high electric fields," Appl. Phys. Lett., vol. 112, no. 6, p. 062101, 2018. gate leakage current only above a relatively high electric field DOI: 10.1063/1.5006249. [13] J. Lutz, H. Schlangenotto, U. Scheuermann, and R. De Doncker, "MOS of ≈7 MV/cm. According to the medium-term reliability test at Transistors and Field Controlled Wide Bandgap Devices," in a wide electric field range, an acceptable failure rate of 3450 Semiconductor Power Devices: Physics, Characteristics, Reliability, 2nd PPM (1 hour at 3 MV/cm, room temperature) for the 100 µm ed., Springer International Publishing AG, pp. 341-390, 2018. DOI: https://doi.org/10.1007/978-3-319-70917-8. diameter MOS capacitors is obtained, which can be further [14] S. Lombardo, J. H. Stathis, B. P. Linder, K. L. Pey, F. Palumbo, and C. reduced to 40 PPM if the extrinsic defects (mechanism I) are H. Tung, "Dielectric breakdown mechanisms in gate oxides," J. Appl. neglected. Long-term TDDB tests over several months have Phys, vol. 98, no. 12, p. 121301, 2005. DOI: 10.1063/1.2147714. [15] P. Fiorenza, A. Frazzetto, A. Guarnera, M. Saggio, and F. Roccaforte, been done for Φ100 MOS capacitors at 7.5 MV/cm, 8.5 MV/cm "Fowler-Nordheim tunneling at SiO2/4H-SiC interfaces in metal-oxide- > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 6 semiconductor field effect transistors," Appl. Phys. Lett., vol. 105, no. 14, [34] M. Krieger, S. Beljakowa, L. Trapaidze, T. Frank, H.B. Weber, G. Pensl, p. 142108, 2014. DOI: 10.1063/1.4898009. N. Hatta, M. Abe, H. Nagasawa, and A. Schoner, "Analysis of interface [16] J. Eriksson, F. Roccaforte, P. Fiorenza, M.H. Weng, F. Giannazzo, J. trap parameters from double-peak conductance spectra taken on n- Lorenzzi, N. Jegenyes, G. Ferro and V. Raineri, "Nanoscale probing of implanted 3C-SiC MOS capacitors," Physica Status Solidi (b), vol. 245, dielectric breakdown at SiO2/3C-SiC interfaces," J. Appl. Phys, vol. 109, no. 7, pp. 1390-1395, 2008. DOI: 10.1002/pssb.200844062. no. 1, p. 013707, 2011, DOI: 10.1063/1.3525806. [35] F. Li, Y.K.Sharma, M.R. Jennings, A. Perez-Tomas, V.A. Shah, H. Rong, [17] K. Yagi, T. Kawahara, N. Hatta, and H. Nagasawa, "‘Switch-Back S.A.O. Russell, D.M. Martin, and P.A. Mawby, "Improved channel Epitaxy’as a Novel Technique for Reducing Stacking Faults in 3C-SiC," mobility by oxide nitridation for n-channel MOSFET on 3C-SiC Mater. Sci. Forum, vol. 527, pp. 291-294, 2006. DOI: (100)/Si," Mater. Sci. Forum, vol. 858, pp. 667-670, 2016. DOI: 10.4028/www.scientific.net/MSF.527-529.291. 10.4028/www.scientific.net/MSF.858.667. [18] J. Eid, I. G. Galben, and S. Saddow, "3C-SiC growth on Si substrates via [36] H. Uchida, A. Minami, T. Sakata, H. Nagasawa, and M. Kobayashi, "High CVD: An introduction," in Physics of Advanced Materials Winter School, temperature performance of 3C-SiC MOSFETs with high channel pp. 281-304, 2008. mobility," Mater. Sci. Forum, vol. 717, pp. 1109-1112, 2012. DOI: [19] F. La Via, A. Severino, R. Anzalone, C. Bongiorno, G. Litrico, M. 10.4028/www.scientific.net/MSF.717-720.1109. Mauceri, M. Schoeler, P. Schuh, and P. Wellmann, "From thin film to [37] K.K. Lee, Y. Ishida, T. Ohshima, K. Kojima, Y. Tanaka, T. Takahashi, H. bulk 3C-SiC growth: Understanding the mechanism of defects reduction," Okumura, K. Arai, and T. Kamiya, "N-channel MOSFETs fabricated on Mat. Sci. Semicon. Proc, vol. 78, pp. 57-68, 2018. DOI: homoepitaxy-grown 3C-SiC films," IEEE Electron Device Letters, vol. 10.1016/j.mssp.2017.12.012. 24, no. 7, pp. 466-468, 2003. DOI: 10.1109/LED.2003.815006. [20] R. Anzalone, A. Serverino, G. D’Arrigo, C. Bongiorno, G. Abbondanza, [38] V. V. Afanas' ev, F. Ciobanu, S. Dimitrijev, G. Pensl, and A. Stesmans, G. Foti, S. Saddow, and F. La Via, "Heteroepitaxy of 3C-SiC on different "SiC/SiO2 interface states: properties and models," Mater. Sci. Forum, on-axis oriented silicon substrates," J. Appl. Phys, vol. 105, no. 8, pp. vol. 483, pp. 563-568, 2005. DOI: 10.4028/www.scientific.net/MSF.483- 084910-7, 2009. DOI: 10.1063/1.3095462. 485.563. [21] R. Yakimova, R. Vasiliauskas, J. Eriksson, and M. Syväjärvi, "Progress [39] A. V. Penumatcha, S. Swandono, and J. A. Cooper, "Limitations of the in 3C-SiC growth and novel applications," Mater. Sci. Forum, vol. 711, high-low C-V technique for MOS interfaces with large time constant pp. 3-10, 2012. DOI: 10.4028/www.scientific.net/MSF.711.3. dispersion," IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 923-926, [22] A. Gupta and C. Jacob, "Selective epitaxy and lateral overgrowth of 3C- 2013. DOI: 10.1109/TED.2013.2237777. SiC on Si – A review," Prog. Cryst. Growth. Ch, vol. 51, no. 1–3, pp. 43- [40] R. Arora, J. Rozen, D.M. Fleetwood, K.C. Galloway, C.X. Zhang, J. Han, 69, 2005. DOI: 10.1016/j.pcrysgrow.2005.10.003. S. Dimitrijev, F. Kong, L.C. Feldman, S.T. Pantelides, and R.D. Schrimpf, [23] N. Hatta, T. Kawahara, K. Yagi, H. Nagasawa, S. A. Reshanov, and A. "Charge trapping properties of 3C- and 4H-SiC MOS capacitors with Schöner, "Reliable method for eliminating stacking fault on 3C-SiC nitrided gate oxides," IEEE Trans. Nuclear Science, vol. 56, no. 6, pp. (001)," Mater. Sci. Forum, vol. 717, pp. 173-176, 2012. 3185-3191, 2009. DOI: 10.1109/TNS.2009.2031604. [24] H. Nagasawa and K. Yagi, "3C-SiC single-crystal films grown on 6-Inch [41] M. Lenzlinger and E. H. Snow, "Fowler‐Nordheim tunneling into Si substrates," Physica Status Solidi (b), vol. 202, no. 1, pp. 335-358, thermally grown SiO2," J. Appl. Phys, vol. 40, no. 1, pp. 278-283, 1969. 1997. DOI: 10.1002/1521-3951(199707)202:1<335::AID- DOI: 10.1063/1.1657043. PSSB335>3.0.CO;2-Y. [42] J. Senzaki, K. Kojima, T. Kato, A. Shimozato, and K. Fukuda, [25] X. Song, J. Biscarrat, A.E. Bazin, J.F. Michaud, F. Cayrel, M. "Correlation between reliability of thermal oxides and dislocations in n- Zielinski, T. Chassagne, M. Portail, E. Collard, and D. Alquier, "Dose type 4H-SiC epitaxial wafers," Appl. Phys. Lett., vol. 89, no. 2, p. 022909, Influence on Physical and Electrical Properties of Nitrogen Implantation 2006, DOI: 10.1063/1.2221525. in 3C-SiC on Si," Mater. Sci. Forum, vol. 711, pp. 154-158, 2012. DOI: [43] U. Schwalke, M. Pölzl, T. Sekinger, and M. Kerber, "Ultra-thick gate 10.4028/www.scientific.net/MSF.711.154 oxides: charge generation and its impact on reliability," Microelectronics [26] F. Li, Y. Sharma, V. Shah, M.R. Jennings, A. Perez-Tomas, M. Myronov, Reliability, vol. 41, no. 7, pp. 1007-1010, 2001. DOI: 10.1016/S0026- C.A. Fisher, D. Leadley, and P.A. Mawby, "Electrical activation of 2714(01)00058-0. nitrogen heavily implanted 3C-SiC(1 0 0)," Applied Surface Science, vol. [44] D. Arnold, E. Cartier, and D. J. DiMaria, "Theory of high-field electron 353, pp. 958-963, 2015. DOI: 10.1016/j.apsusc.2015.06.169. transport and impact ionization in silicon dioxide," Physical Review B, [27] Y. K. Sharma, F. Li, M.R. Jennings, C.A. Fisher, A. Perez-Tomas, S. vol. 49, no. 15, pp. 10278-10297, 1994. DOI: Thomas, D.P. Hamilton, S.A.O. Russell, and P.A. Mawby "High- 10.1103/PhysRevB.49.10278. temperature (1200–1400°C) dry oxidation of 3C-SiC on silicon," Journal [45] M. Beier-Moebius and J. Lutz, "Breakdown of gate oxide of 1.2 kV SiC- of Electronic Materials, vol. 44, no. 11, pp. 4167-4174, 2015. DOI: MOSFETs under high temperature and high gate voltage," in PCIM 10.1007/s11664-015-3949-4. Europe 2016, pp. 1-8. [28] R. Esteve, A. Schoner, S. A. Reshanov, C. M. Zetterling, and H. [46] P. A. Losee, K. Matocha, S.D. Arthur, J. Nasadoski, Z. Stum, J.L. Garrett, Nagasawa, "Comparative study of thermally grown oxides on n-type free M. Schutten, G. Dunne, and L. Stevanovic, "DC and transient standing 3C-SiC (001)," J. Appl. Phys, vol. 106, no. 4, pp. 044513-4, performance of 4H-SiC double-implant MOSFETs," IEEE Trans. 2009. DOI: 10.1063/1.3204642. Electron Devices, vol. 55, no. 8, pp. 1824-1829, 2008. DOI: [29] B. Zippelius, M. Hauck, S. Beljakowa, H.B. Weber, M. Krieger, H. 10.1109/TED.2008.926592. Nagasawa, H. Uchida, G. Pensl, and A. Schoner, "Dependence of the [47] J. Sune, "New physics-based analytic approach to the thin-oxide channel mobility in 3C-SiC n-MOSFETs on the crystal orientation and breakdown statistics," IEEE Electron Device Letters, vol. 22, no. 6, pp. channel length," Mater. Sci. Forum, vol. 717, pp. 1113-1116, 2012. DOI: 296-298, 2001. DOI: 10.1109/55.924847. 10.4028/www.scientific.net/MSF.717-720.1113. [48] J. H. Stathis, "Percolation models for gate oxide breakdown," J. Appl. [30] J. Eriksson, M. H. Weng, F. Roccaforte, F. Giannazzo, S. Leone, and V. Phys, vol. 86, no. 10, pp. 5757-5766, 1999. DOI: 10.1063/1.371590. Raineri, "Toward an ideal Schottky barrier on 3C-SiC," Appl. Phys. Lett., [49] J. W. McPherson and D. A. Baglee, "Acceleration factors for thin gate vol. 95, no. 8, pp. 081907-3, 2009. DOI: 10.1063/1.3211965 oxide stressing," in in Proc. 23rd Annu. IEEE Int. Rel. Phys. Symp., pp. [31] F. Li, Y. Sharma, D. Walker, S. Hindmarsh, M.R. Jennings, D. Martin, 1-5, 1985. DOI: 10.1109/IRPS.1985.362066. C.A. Fisher, P.M. Gammon, A. Perez-Tomas, and P.A. Mawby, "3C-SiC [50] J. Senzaki, A. Shimozato, and K. Fukuda, "Acceleration factors in transistor with ohmic contacts defined at room temperature," IEEE acceleration life test of thermal oxides on 4H-SiC wafers," Mater. Sci. Electron Device Letters, vol. 37, no. 9, pp. 1189-1192, 2016. DOI: Forum, vol. 556-557, pp. 635-638, 2007. DOI: 10.1109/LED.2016.2593771. 10.4028/www.scientific.net/MSF.556-557.635. [32] H. Nagasawa, M. Abe, K. Yagi, T. Kawahara, and N. Hatta, "Fabrication of high performance 3C-SiC vertical MOSFETs by reducing planar defects," Physica Status Solidi (b), vol. 245, no. 7, pp. 1272-1280, 2008. DOI: 10.1002/pssb.200844053. [33] T. Gutt, T. Malachowski, H. M. Przewlocki, O. Engstrom, M. Bakowski, and R. Esteve, "Investigation of gate edge effect on interface trap density in 3C-SiC MOS capacitors," Materials Science and Engineering B- Advanced Functional Solid-State Materials, vol. 177, no. 15, pp. 1327- 1330, 2012. DOI: 10.1016/j.mseb.2012.03.007.