This is the accepted version of the article: Nafria, Montserrat; Martin Martinez, Javier; Rodriguez Martinez, Rosana; [et al.]. «Flexible setup for the measurement of CMOS time-dependent variabil- ity with array-based integrated circuits». IEEE Transactions on Instrumen- tation and Measurement, Vol. 69, Issue 3 (March 2020), p. 853-864. DOI 10.1109/TIM.2019.2906415 This version is available at https://ddd.uab.cat/record/248833 under the terms of the license Flexible Setup for the Measurement of CMOS Time- dependent Variability with Array-based Integrated Circuits Javier Diaz-Fortuny1, Pablo Saraza-Canflanca2, Rafael Castro-Lopez2, Elisenda Roca2, Javier Martin-Martinez1, Rosana Rodriguez1, Francisco V. Fernandez2 and Montserrat Nafria1. 1 Electronic Engineering Department (REDEC) group. Universitat Autònoma de Barcelona (UAB), Barcelona, (Spain). 2 Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, (Spain). Abstract—This paper presents an innovative and automated transient effect, which consists in current fluctuations between measurement setup for the characterization of variability effects two or more differentiated levels. in CMOS transistors using array-based integrated circuits, Today, all TDV phenomena are a serious concern because through which a better understanding of CMOS reliability could their inherent variability impact on circuit and system be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: variability in advanced integration nodes [12],[13]. Therefore, testing a very large number of devices accurately but, also, in a statistical modeling and characterization of the device timely manner. The setup consists of software and hardware degradation produced by these sources of variability is components that provide a user-friendly interface to perform the mandatory. This degradation has been captured in several statistical characterization of CMOS transistors. Five different models reported so far, such as the Probabilistic Defect electrical tests, comprehending time-zero and time-dependent Occupancy (PDO) model [14], representing a key step in variability effects, can be carried out. Test preparation is, with the variability-aware design methodologies [15]. One major described setup, reduced to a few seconds. Moreover, smart challenge related to the intrinsic random nature of the parallelization techniques allow reducing the typically time- variability mechanisms is that a large number of transistors consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology should be characterized to get statistically significant results. and practice of measurement of CMOS time-dependent Thus, when thousands of devices should be tested, traditional variability, as well as the development of appropriate on-wafer device testing techniques based on serial device measurement systems and components used in efficiently characterization result in unfeasible testing times. In this generating and acquiring the necessary electrical signals. scenario, integrated circuits (IC) with transistor arrays have been proposed for massive device characterization of TZV [16] Keywords— Variability, Aging, BTI, HCI, RTN, Device and aging (BTI/HCI) [17]-[23], to reduce test times Modelling, Automated characterization lab. significantly. Array-based ICs for RTN characterization have I. INTRODUCTION been also developed [24],[25]. Recently, the first array-based IC enabling the characterization of all these effects has been In the last decades, CMOS technologies have experienced a proposed [26],[27]. steady scaling predicted by Moore’s law, hugely improving the Despite the advantages over conventional wafer-based device performances. In this dive into the nanometer scale, techniques, array-based solutions bring new challenges (e.g., IR dealing with (time-zero) variability (TZV) has been a constant drops on internal chip metal lines, large number of devices or struggle [1]. However, while manufacturing process variations individual device access), critical not only for the design of the have been kept under control (by steadily innovating in IC itself but also for the way in which it will be tested. manufacturing tools and improvement strategies), random Therefore, efficient and accurate setups must be developed to variations (like Random Discrete Dopants, Line Edge provide users with a hardware and software solution for fully- Roughness, Metal Grain Granularity, …), arising from the automated device-level variability characterization. discreteness of charge and matter granularity, have become a In this scenario, this paper presents a flexible critical concern for circuit design in advanced nodes, since they characterization setup that consists in a complete laboratory cause fluctuations that result in transistor electrical parameter instrumentation system and a fully-automated characterization mismatches between identically designed devices (e.g., software, together with a graphical user interface (GUI), to threshold voltage mismatch) [2],[3]. Though (planar or 3D) SOI fulfill the hardware and software requirements for a trustworthy technologies mitigate this problem, it remains an important and straightforward transistor characterization. concern [4],[5]. The rest of this paper is organized as follows. A review of Another source of transistor variability, known as time variability phenomena affecting CMOS transistors, along with dependent variability (TDV), appears during circuit operation, the suitable characterization procedure, is explained in Section and can be temporary or permanent. TDV phenomena, like Bias II. Section III briefly shows the features of the fabricated 65- Temperature Instability (BTI) [6], Hot Carrier Injection (HCI) nm CMOS array-based chip for which the measurement setup [7], [8], or time-dependent dielectric breakdown (TDDB) [9], has been developed. A detailed description of the measurement which have been intensively investigated in the last decades, are hardware elements employed for the massive characterization reflected in the progressive degradation of the transistor of the chip devices is given in Section IV. Section V describes parameters over time. All these phenomena become the design of the characterization software. Illustrative results intrinsically stochastic at the nanometer scale. Another TDV obtained from the chip with the proposed setup are presented in phenomenon is the Random Telegraph Noise (RTN) [10], [11] section VI and, finally, the conclusions are drawn in Section VII. degraded transistor parameters and computing their shifts from their initial pristine values [6]. The SM technique used in this II. VARIABILITY CHARACTERIZATION IN CMOS TRANSISTORS work follows three steps: A. I-V characterization 1) Initial device characterization: measurement of the For the characterization of transistor variability, it is critical pristine IDS-VGS curve (see Section II.A) to extract the device to obtain the transistor parameters, such as threshold voltage parameters before the application of any kind of stress. (Vth0) or mobility (µ0), in order to assess their variations. The 2) Stress: BTI and HCI are long-term aging processes that transistor parameters are extracted from the drain current vs. take place while devices operate within their nominal operating gate-source voltage (IDS-VGS) and the drain current vs. drain- voltages. Thus, in order to be able to characterize both aging source voltage (IDS-VDS) characteristics processes in relatively short and affordable times, the devices must be subject to accelerated stress processes that consist in B. Random Telegraph Noise characterization the application of high temperatures and/or overvoltages, e.g., Performance of short channel devices is strongly influenced twice the nominal supply voltage, to the device terminals by a random switching of IDS between two or more levels along [7],[39]-[41]. For BTI characterization, a high VGS and VDS = time. These current fluctuations are related to the capture and 0V are set, whereas, for HCI, VDS is set at high values. emission of charge carriers by oxide and interface traps, 3) Measurement: the evolution of the drain current with time showing a large dependence on device biasing and temperature. IDS(t) is registered right after the stress is removed, the exact The RTN phenomenon has been recognized as a significant moment at which the parameters of the stressed devices start variability source since it is responsible of device parameter recovering. During the IDS(t) measurement, the discharges (i.e., shifts that increase inversely with area scaling [28]. recoveries) of the traps previously charged in the stress phase The standard RTN characterization procedure consists in are measured and characterized. The sampling rate during the continuously measuring the IDS current while maintaining a measurement must be as high as possible in order to capture fast constant VDS and VGS bias voltage. Sufficient accuracy of the current events that may occur after the stress phase. At the end current measurement is required since the RTN-induced current of each IDS(t) measurement, an additional IDS-VGS variation may amount to just a few nanoamps. The time characterization is carried out for a complete analysis of the required for a statistically sound characterization of RTN depends on the trap(s) intrinsic capture/emission time transistor parameter degradation. constants, which span several orders of magnitude. Most As the device parameter degradation depends on the stress previous efforts have been directed to RTN analysis methods time, several SM cycles are applied sequentially to the samples, (e.g., [29]) or to the necessary timings for a meaningful where the time on each stress cycle is typically increased estimation of time constants [30]. Although these aspects exponentially. On the other hand, the elapsed time between the deserve attention, only recently array-based solutions devised stress (second step) and measurement (third step) should be as to satisfy the required statistical characterization have been short as possible and preferably equal for all tested devices reported [24]-[27]; bringing new challenges, e.g., automation, because, as soon as the stress is removed, the recovery behavior individual device access, or accurate control of bias voltages for of the threshold voltage begins. an accurate characterization of the bias voltage dependence of The characterization of the different phenomena presented in time constants. this Section, together with the adopted array-based strategy, C. BTI and HCI characterization leads to a set of instrumentation and measurement challenges that the experimental setup should address: BTI and HCI are both aging phenomena that produce a • Massive characterization of many devices is needed due to gradual shift of the device parameters over time: mainly an the stochastic nature of TDV in nanometer-scale increase of the threshold voltage (Vth0), but also a decrease in technologies. the channel mobility (µ0). Similar to RTN, the capture and • Transistors with different channel geometries should be emission of charges to/from traps are believed to be behind characterized to study the dependence of TDV phenomena these shifts, with charges being stochastically trapped when a with device size. certain voltage is applied (therefore increasing the threshold voltage), and emitted when the voltage decreases (therefore the • Accurate electrical characterization (which results in the threshold voltage starts recovering its original value). Such need for canceling leakage currents, applying accurate shifts depend on the local temperature as well as on the (time- voltages to the device terminals, minimizing the noise in varying) voltages applied. The shifts can lead to severe, even the measurement lines and ensuring stable biasing) is fatal, circuit performance degradation. Therefore, in order to required in order to correctly study the dependence of TDV predict and mitigate these effects, the study of BTI and HCI with the bias conditions. phenomena has a renewed interest in nanometric technologies • Accurate thermal characterization over a broad range of [31],[32]. Proper modelling [14], model parameter extraction temperatures is essential, since the TDV phenomena [33],[34] and simulation strategies [35]-[37] are essential not strongly depend on temperature. only to implement appropriate variability-aware design • Characterization times must be affordable. techniques but for proper design of runtime compensation • Due to the large number of devices and the long strategies [15],[38]. characterization times, the control of the test process and BTI/HCI transistor characterization commonly uses a stress- data analysis must be fully automated. measurement (SM) technique that allows extracting the These requirements are addressed by the combined power of an experimental setup composed of a hardware part (Section IV) and a software part (Section V) and the array-based IC, named ENDURANCE, reported in [26],[27], and whose major characteristics impacting the experimental setup are reviewed in Section III. III. TEST STRUCTURES The ENDURANCE chip is capable of characterizing TZV, BTI, HCI and RTN phenomena [26],[27]. The chip was fabricated in a 1.2-V, 65-nm CMOS technology with an area of 1800x1800 μm2. It includes NMOS and PMOS transistors arranged in two independent arrays, with a total of 3,316 regular threshold voltage transistors, here forth known as the devices under test (DUT). Transistors with different width and length values have been included Figure 1. Schematic representation of the laboratory setup. Each DUT of the arrays is surrounded by a digital control circuitry, conforming what is called a unit cell of the array. The control circuitry determines how the terminals of the DUT (gate To avoid aging or degradation of the 8 TGs included in each and drain terminals) are connected to the external chip pads. unit cell due to the overvoltages applied during the stress mode, The chip, which is encapsulated in a JLCC68 package, these are designed with IO transistors capable of withstanding includes 64 pads, 36 corresponding to analog signals that voltages up to 3.3V without significant degradation during the connect to the DUT terminals, and 28 pads corresponding to experiments. digital signals that are connected to the control circuitry of the IV. HARDWARE SETUP unit cells. Each array is subdivided in two subarrays that have independent analog signals connected to external pads. Three An experimental setup has been developed for the different paths connect the DUTs with the analog pads: a characterization of the ENDURANCE chip. A schematic measurement path, a stress path and a stand-by path, and the representation of this measurement setup is shown in Fig. 1. It gate and drain terminal of each DUT are connected through consists of the following elements: switches or transmission gates (TG) to all three paths. The drain • A full-custom printed circuit board (PCB), where the terminal has Force and Sense [42] connections for both the ENDURANCE IC is inserted for DUT measurements. measurement and the stress paths, so a total of 5 analog signals • The Keysight Semiconductor Parameter Analyser (SPA) are connected to this terminal. Since negligible current flows model B1500A. The system has 4 High Resolution Sense through the gate terminal, it has no Force-&-Sense connection, Measurement Units (HRSMU), with Force-&-Sense so only 3 analog signals are connected to this DUT terminal. outputs for precise voltage application and current The switches connecting the three paths are controlled by the measurement [42]. The analog signal pads are connected to digital control circuitry of the unit cell. Depending on the value the HRSMUs, so that the voltage can be set, and, if of the digital control signals applied, each unit cell will be set necessary, the currents can be measured [43]. in one out of the following four operation modes (OM): • The Agilent E3631A power supply for PCB (and (i) Measurement mode: it is designed to measure I-V subsequently IC) biasing using a 5V/1A DC biasing characteristics, RTN transient effects and post-stress BTI/HCI voltage [44]. phenomena. For these tests, only low voltages (i.e. from 0V to • The T-2650BV Thermonics precision temperature system 1.2V) are allowed. The physical paths that connect to the DUT with a temperature ranging from room temperature to terminals are: the drain measure path (designed with Force-&- 120ºC [45]. Sense lines to compensate for the IR drops) and the gate • A USB Digital Acquisition System (DAQ), model USB- measure path. (ii) Stress mode: it is designed to apply an overvoltage, i.e., from 1.2V to 3.3V, to the gate and/or drain terminals during the stress phase of BTI and HCI tests. The physical on-chip paths for this mode are the drain stress path (designed with Force-&- Sense lines), and the gate stress path. The availability of separate stress and measurement analog paths for the drain terminal enables the implementation of smart parallelization schemes, as detailed in Section V. (iii) Stand-by mode: this mode sets all voltage differences of the DUT terminals at 0V when neither measurement nor stress are conducted, and is intended to avoid any device degradation while other devices are being measured or stressed. iv) Off mode: this mode opens all switches or TGs of the unit cell, disconnecting the DUT from the analog paths. The off OM serves as a bridge between the stand-by mode and the measure/stress modes to prevent short-circuits. It is also used to disconnect non-functional DUTs. Figure 2. Top layout of the PCB. 6501 from National Instruments, equipped with 24 digital through them is negligible (which happens with the gate IO channels, that provides the digital signals for the IC measure (GM), drain measure sense (DMS) and drain stress control [46]. sense (DSS) lines), or are used for stressing the DUTs and the • A personal computer (PC) equipped with Matlab®. current is not measured (which happens with the gate stress The Agilent E3631A power supply, the Keysight B1500A (GS) and drain stress force (DSF) lines). These signals are SPA and the Thermonics temperature system T-2650BV are physically multiplexed along the four DUT subarrays, so that connected using an IEEE 488 General Purpose Interface Bus only five additional triaxial connectors are necessary, as seen at (GPIB) in order to send and receive data during tests the right side of the PCB in Fig. 2. executions. For the communication with the DAQ, a 3.0 USB Finally, a squared area surrounding the IC socket has been connection is used. left free of connectors. This area is used to place the head of the The PCB has been designed to provide easy access to the Thermonics system over the chip, so that temperature inside the chip, but preserving the accuracy of the measurements. Figure head (and therefore, the temperature of the chip) can be 2 shows the PCB layout composed of 3 main blocks: the input controlled. digital block (Fig. 2, section A), the biasing circuitry block (Fig. 2, section B) and the socket and connectors block (Fig. 2, V. SOFTWARE TOOL section C). These blocks are explained in more detail below. For the tests described in Section II, thousands of properly scheduled instructions are needed to control the hardware setup A. Biasing circuitry block described in the previous section. Therefore, the need for Three precise and stable biasing voltages are needed for the automating the generation of instructions for the control of the ENDURANCE chip. For this purpose, a dedicated biasing hardware setup becomes patently clear. To this end, a software circuitry that uses three CMOS high precision voltage toolbox that generates all necessary GPIB and DAQ regulators has been implemented in the PCB circuitry (section instructions named TARS (A Toolbox for Statistical Reliability B in Fig. 2). This circuitry provides, from a single 5V-1A DC Modelling of CMOS Devices) has been implemented using power supply voltage, the biasing voltages of all digital circuits Matlab® scripting language [47]. This toolbox features several of the chip (1.2V), of the digital IO pads (2.5V) and of the user-friendly GUIs (illustrated in Fig. 3) to facilitate the transmission gates and analog pads that enable stress voltages definition of measurement tests. up to 3.3V. A. Architecture B. Input digital block The transformation of the test parameters specified by the This block (located in section A in Fig. 2) is in charge of user in Fig. 3 into a set of GPIB commands for instrumentation receiving the set of digital signals generated by the DAQ for the control as well as DAQ commands for IC control, follows a chip control. These signals are connected to the PCB through a modular approach with three main modules and the scripts for 32-pin Insulation-Displacement Connector (IDC). A set of 5 the communication between them. These modules are: digital electromagnetic isolator chips are used to transfer these (i) Test plan generation: this module receives the digital signals to an isolated PCB power domain where the IC information about the user-defined tests and generates a is located so that any noise coming from the PC power domain script containing a specific test plan. This plan consists of a is reduced. This improves the set-up capabilities, especially for low-level current measurements. C. Socket and connectors block This block of the PCB includes a 68-pin zero-insertion force socket, where the ENDURANCE chips are inserted for testing, and different triax connectors that provide access to the output signal pads of the four arrays through the B1500 HRSMUs triaxial connectors and cables. The socket allows a large number of chip insertions, ensuring the durability of the test system. As mentioned in Section III, each DUT terminal (i.e. drain and gate terminals) is connected to three different paths that can be accessed from independent analog pads for each array. Stand-by pads are physically connected to the analog ground or analog power supply voltage, depending on the type of DUT of the subarrays (N- or P-type transistors, respectively). The other pads are accessible through triaxial connectors. For those pads where current has to be measured, i.e. the drain measure force output pads of the four subarrays (DMF_N1, DMF_N2, DMF_P1 and DMF_P2 in Fig. 2), a built-in guard has been implemented between their triaxial connector and the IC socket pin. This guard is connected to the guard shield provided by the triax cables of the B1500 SPA, extending the isolation of the measured current to the PCB. This built-in guard has not been implemented in the other output pads because the current Figure 3. The Test Setup & Monitoring GUI of the TARS toolbox. only one DUT can be measured at a time to assess its degradation. The PSPM technique [48],[49] deals with this constraint by delaying the SM sequence of each DUT with respect to the previous one, resulting in a “place-and-check” algorithm that partially executes simultaneous (parallel) stress phases and pipeline measurement phases depending on the Figure 4. Illustrative example of the ADPSPM technique with 5 DUTs duration of the first stress period. This is done by delaying a during a 4-cycle SM test. C1 corresponds to the first SM pattern and complete number of SM cycles, which essentially means C2 to the second. The application of the ADPSPM algorithm shows repeating the PSPM tests in series until all DUTs are tested. that the measurement phases are not overlapped at any time thanks to Therefore, the PSPM technique becomes inadequate for certain the addition of SB periods. values of the initial stress time and number of SM cycles. proper sequence of the electrical tests to be applied to each The ADPSPM parallel testing technique utilizes stand-by DUT and the range of test conditions. (SB) periods that are introduced between certain measurement (ii) Elementary instruction generation: this module and stress phases to make the necessary room to accommodate transforms each command of the test plan into the set of any number of DUTs. Obviously, the length of the SB periods elementary actions that implement such command. must be accounted for during the postprocessing of (iii) Test execution: this module reads each elementary measurement data to generate model parameters since the instruction and generates and sends the corresponding GPIB devices may continue their recovery during such period. As commands to the instrumentation and the IC control depicted in Fig. 4, in order to achieve an accurate and efficient instructions to the DAQ. SM parallel test, the algorithm handles each test cycle These three modules are described in detail in the following individually. In the first cycle (C1 polygon in Fig. 4), the SM subsections. But before doing so, it is important to bring out a pattern of each DUT is delayed, like in the PSPM approach, in major advantage of array-based ICs over conventional probe order to ensure that the measurement phases in all DUTs are stations: the possibility of executing parallel stress techniques to characterize HCI and BTI of hundreds of devices. However, pipelined. Once all the SM patterns of cycle C1 have been it is not sufficient that an array-based IC enables that possibility, temporarily allocated, the algorithm starts the distribution of the but more importantly, that the experimental setup must next cycle (C2 polygon in Fig. 4). The ADPSPM algorithm accurately and efficiently exploit such capability. The setup ensures that the last measurement phase of cycle C1 (for described in this paper uses the stress parallelization technique DUT#5 in Fig. 4) does not overlap with the first measurement named all-DUT-parallel-stress-pipeline measurements phase of cycle C2 (for DUT#1), shown in Fig. 4 with a dashed (ADPSPM), which drastically reduces the total aging test time arrow, by inserting the necessary standby periods (SB). Thus by stressing devices in parallel while maintaining sequential the ADPSPM technique can accommodate any number of DUT measurement. This technique is directly involved in the DUTs. generation of the appropriate test plan and, hence, it is described To illustrate the advantages of this technique, it is in the next subsection. interesting to perform a study of the time complexity of the characterization process. Fig. 5 shows the characterization time B. Stress parallelization per device as a function of the number of DUTs for three Parallelization techniques are used to dramatically speed up different combinations of the number of SM cycles, the aging tests. In this regard, the stress can be parallelized but measurement time, and duration of the stress periods. The Figure 5. Total test time per device as a function of the number of devices for SERIAL, PSPM and ADPSPM techniques considering a measurement time of 100s and an exponential increase of stress time in SM cycles (base 10) with (a) 5-cycle SM aging test starting with a stress time of 1s, (b) 4-cycle SM aging test starting with a stress time of 10s and (c) 3-cycle SM aging test starting with a stress time of 100s. measurement time of the SM cycles is 100s in all cases. The C. Test plan generation three cases use 5, 4 and 3 SM cycles, being the duration of the From the user-specified tests, e.g., those shown in Fig. 3, a first stress period 1s, 10s and 100s, respectively, and test plan must be built. The test plan contains information about exponentially increasing in the successive cycles. The blue each test performed to each DUT. This information includes the diamonds represent the time complexity of the SERIAL test, a DUT identification, the corresponding test, i.e., IDS-VGS, IDS- brute-force approach in which the devices are characterized one VDS, RTN or BTI/HCI, and the variables for the particular tests, at a time, by applying the full sequence of SM cycles. The test i.e., delay time, voltages, temperature, etc. The test plan is of the following DUT does not start until all SM cycles of the written in a script, whose possible codes are displayed in Table previous device have finished. This implies that the test time per device amounts to the sum of stress times and measurement I for each type of test. times of all SM cycles. If we consider the place-and-check For the generation of the test plan, the algorithm described PSPM technique for the conditions shown in Fig. 5(a) in red by the flow diagram of Fig. 6 is executed. The algorithm is squares, no parallel stress can be applied because the initial divided into three different branches: the I-V measurement stress time of 1s only allows to test one single device at a time, branch, which is dedicated to IDS-VGS and IDS-VDS test plan thus overlapping with the SERIAL testing time (see inset in Fig. generation, the RTN test branch, and the BTI/HCI aging 5(a)). This means that no time improvement when compared branch, which applies the ADPSPM technique to optimally with SERIAL test can be achieved. On the contrary, the allocate stress, measurement and stand-by periods for all ADPSPM technique clearly shows a fast decrease of the test devices. Together with this algorithm, test plan instructions are time per device when increasing the number of devices, as scheduled with the goal of keeping equal stress/measurement shown with the orange circles. In Fig. 5(b), the initial stress time periods for all devices and keeping an equal and minimum is set to 10s allowing the PSPM technique to parallelize only 2 delay between the stress and the measurement periods of each devices whereas in Fig.5(c) the initial stress time is set to 100s device. and up to 10 devices can be stressed in parallel with the PSPM For the sake of illustration, let us consider a test example technique. Correspondingly, the test time per device is reduced with just 5 devices where the test plan consists of (i) measuring to one half or one tenth of the SERIAL procedure, but this 2- the IDS-VGS curve of all devices, (ii) executing an RTN test with device or 10-device parallel scheme must be repeated until all a single VGS/VDS condition and a measurement time of 100s, for devices are measured. Also in these cases, the ADPSPM all selected devices and, finally, (iii) running a 5-cycle SM BTI technique reveals a significant test time reduction compared to measurement with measurement time of 100s and exponentially the SERIAL and PSPM techniques, by parallelizing the stress (base 10) increasing test times starting at 1s using the ADPSPM phases whenever possible while maintaining the measurement parallelization algorithm. The resulting test plan script, shown channel occupied the maximum time (see Fig. 4). partially in Fig. 7, contains the information that defines all these As stated above, only one DUT can be measured at a time. tests. Lines 2 to 5 show an excerpt of the IDS-VGS test plan. Line Therefore, even if we ignore the stress times and the necessary parallelization, just the measurement periods imply the number 2 sets DUT#1 in measurement mode with a sweep in VGS. Then, of cycles x the measurement time per cycle. This IDEAL time is indicated as a continuous black line in Fig. 5. It represents an unreachable limit of the test time per device. It can be checked in Fig. 5 that in all test situations, the ADPSPM technique tends asymptotically to the IDEAL time when the number of DUTs increases. Figure 7. Example of a test plan including IDS-VGS, RTN and BTI Figure 6. Flow diagram of the test plan generation. script lines. TABLE I CODES AND VARIABLES OF TEST PLAN SCRIPT AND ELEMENTARY INSTRUCTION SCRIPT Test plan columns #5 OM Electrical #1 #2 #3 #4 OM #6 #7 #8 #9 #10 code test (s) (integer) (ASCII) (ASCII) (V) (V) (V) (V) (integer) (integer) Initial IDS-VGS Time DUT # PMOS/NMOS ME 33 VD Final VG -- Step VG VG IDS-VDS Time DUT # PMOS/NMOS ME 44 Initial VD Final VD Initial VG Final VG Step VG RTN Time DUT # PMOS/NMOS ME 20 VG VD -- -- -- BTI Time DUT # PMOS/NMOS ME/ST 22/11 VG VD -- -- -- HCI Time DUT # PMOS/NMOS ME/ST 23/11 VG VD -- -- -- Stand-by Time DUT # PMOS/NMOS SB 0 VG VD Elementary instruction columns #1 #2 #3 #4 #5 #6 #7 (s) (integer) (ASCII) (ASCII) (integer) (V) (V) GPIB/DAQ Test time DUT # PMOS/NMOS OM OM code VG VD S variables the DUT is set in stand-by mode so that it does not suffer any must undergo a 100s measurement period. But 1 second before degradation. Notice that the delay time in line 3 (first column) the measurement stage finishes, DUT#2 is set in stress (line 18). is 0, meaning that the following script line can be immediately After the measurement of DUT#1 finishes it is set in stand-by executed. The same sequence is applied to the second DUT (line 20). Thanks to setting DUT#2 in stress mode just the (lines 4-5) until we complete all devices. Lines 9 to 12 are an required stress time before the measurement of DUT#1 finishes, excerpt of the RTN characterization. Each device is DUT#2 is ready for measurement just after DUT#1. The same sequentially measured for 100 seconds and set at stand-by mode procedure is sequentially applied to the rest of devices. When after each measurement. For the implementation of the test plan the allocation of the first SM cycle finishes, then, the second of the BTI characterization experiment, the ADPSPM one starts with the first device. Notice that the stress period of algorithm in Section V.B is executed. Lines 16 to 38 are an the second cycle is 10s. Therefore, 10s before the measurement excerpt of the first BTI script lines of the test plan. Line 16 sets of DUT#5 finishes (line 33), the stress of DUT#1 is activated the first device in stress mode for one second. Then, the device (line 34). This way, when the measurement of DUT#5 concludes, also does the stress time of DUT#1 and this device is ready for measurement (line 38). Therefore, we achieve two goals: maximum efficiency as the instruments are taking measurements the maximum possible time, and short and equal delay between stress and measurement. D. Elementary test instruction generation The purpose of the test plan is to establish the set and sequence of test actions that have to be performed. The test actions have to be executed through the GPIB commands controlling the different instruments and the control commands of the DAQ for properly selecting and setting the DUTs. However, each line of the test plan script may involve different setting conditions that have to be sequentially established, e.g., each sampling point of the IDS-VGS curve of the test plan line is defined by a different gate voltage. Therefore, this second module transforms the test plan script into a set of sequential elementary instructions. Figure 8 shows an excerpt of the elementary instruction script obtained from the test plan in Fig. 7. Each elementary instruction contains the information to set instruments and DUTs at the correct configuration. For instance, in the case of an RTN experiment, the variables that define the complete experiment are the test duration time, the temperature, the biasing voltages, the gate voltage and the drain voltage (see Table I, GPIB/DAQ variables row). In the case of an IDS-VGS curve, each sampling point of the sweep is defined by its timing, the drain voltage and the gate voltage. These variables will later be used to construct the GPIB commands that will be sent to the instrumentation and the DAQ commands Figure 8. Example of the elementary test instruction script. that will be used to control the IC. Figure 10. IDS(t) trace measurement after BTI stress executed following the 4-step process when switching from ST to ME. DMF path to capture the current leakages happening in the path to the DUT drain (especially those coming from the TGs in that path). This leakage current will be used to calibrate the DUT current measurement. 3. IDS channel measurement: the current through the measurement path is captured while the DUT still remains in its previous OM (i.e., stress OM), before digitally Figure 9. Flow diagram of the test execution module. changing the OM code of the DUT unit cell. At this step, the drain/gate DUT terminals are still connected to the E. Test execution stress path. This step is obviously skipped if there was not a previous ST phase, e.g., RTN or I-V characterization. The test execution module, illustrated in the flow diagram in 4. IDS(t) DUT measurement: after starting the measurement, Fig. 9, reads and executes the elementary test instruction script the OM code of the DUT unit cell is digitally changed to line by line, converting the test variables into the corresponding ME mode and the Drain/Gate DUT terminals are GPIB and DAQ commands, and sending these to the physically switched to the measurement paths. This measurement instruments and the data acquisition system. switching procedure ensures that the time gap while The engine first analyses if the currently selected DUT must changing to the measurement OM will remain minimum be changed. If this is the case, the module sends the and equal for all DUTs involved in the test. The current is corresponding row and column matrix addresses of the new measured for the requested time, except in a I-V DUT to the serial chip interfaces through the DAQ. Then, it characterization in which a single current value is activates the selected operation mode (OM) by connecting the measured for the current bias voltage. drain and gate DUT terminals to the required analog IC paths. Figure 10 illustrates the measurement procedure during any The same operation is performed if the DUT is not changed but measurement execution. The figure shows how the first a new OM code must be applied to the current DUT. measurement points represent only leakage because the DUT is After the appropriate DUT is activated and the OM set, the still connected to the stress lines, and how after the leakage test execution module extracts the VGS and VDS voltages and current measurement is done, the DUT OM is set to the sends the appropriate commands to start a stress (ST) or a measurement mode. measurement (ME) phase: For the sake of illustration, when IDS-VGS, RTN and BTI tests (i) Stress: the stress biasing voltages are set to the drain and are specified for 100 DUTs, a test plan with 2,500 lines is gate HRSMUs and no current is measured. The stress biasing generated. Execution of this test plan produces 20,800 voltages selected for the first time will be kept until the end of elementary test instructions that trigger the same number of the selected test ensuring that all DUTs connected in parallel GPIB commands as well as 2,300 instructions for the DAQ. are stressed in the same conditions and without interruptions After the set of test experiments specified in the test plan are during the complete test duration. completed, a secure shut down protocol is initiated to prevent (ii) Measurement: the biasing voltages of this mode can be any electrical damage to the IC. First, a general RESET signal changed each time a DUT is set into the measurement OM is sent to all unit cells in order to set the secure stand-by because only one DUT will be measured at any time. The test operation mode for all DUTs; second, all SPA HRSMU output execution protocol executes the measurement in 4 steps to have terminals are set as open circuits; third, the PCB biasing voltage a minimum time gap between ST and ME phases and to set by the power supply is removed, and, finally, the GPIB compensate the current leakage of the IC for the particular test connections with the power supply and the B1500A SPA are conditions, i.e., DUT biasing and physical location. These four terminated. steps are: 1. PAD biasing: the algorithm biases the drain and gate VI. EXPERIMENTAL RESULTS measure lines (DMF, DMS and GM in Fig. 2). This section will show some illustrative experimental 2. Current calibration through leakage measurement: a results obtained for pristine PMOS transistors using the leakage current measurement is performed through the Figure 13. Several recovery traces from a massive BTI test involving Figure 11. 784 PMOS |IDS|-|VGS| curves measured for the eight 100 transistors with W=80nm and L=60nm, showing discrete current available geometries in the ENDURANCE IC. The legend indicates recovery steps. the W/L ratio of each device. variability tests. The system has been used to characterize the proposed hardware setup together with the control software and 65-nm transistors of the ENDURANCE IC, the first of its kind the use of the ADPSPM parallelization technique. to enable TZV and pipelined TDV characterization, including Figure 11 shows a complete TZV IDS-VGS test executed over HCI. The measurement setup enables several tests: ramped 784 devices involving 8 different geometries. Each IDS-VGS voltages (IDS-VGS, IDS-VDS), RTN measurements, and BTI and curve shown in Fig. 11 has been obtained by sweeping the |VGS| HCI aging evaluations. These tests can be defined in a matter bias voltage from 10mV to 1.2V while maintaining the |VDS| of seconds and thousands of commands are automatically voltage at 100mV. The results show a different current level and generated for instrumentation and chip control. The described a large TZV for each geometry. measurement setup in combination with the ENDURANCE IC, Figure 12 shows several measured RTN traces where each empowered by the ADPSPM algorithm, allows the application device shows unique RTN behavior. For these RTN of smart stress parallelization techniques to an unlimited measurements, the test plan has been created with |VGS| = 0.5V number of devices. This testing technique smartly overlaps the and |VDS| = 0.1V with a measurement time of 100s and a stress phases of the aging tests, reducing the measurement time sampling rate of 500 samples per second for each device. from years to days. Figure 13 shows some of the measurement traces extracted from a BTI characterization test executed using the ADPSPM ACKNOWLEDGEMENTS parallelization technique involving 100 PMOS DUTs. The This work has been supported by the TEC2016-75151-C3-R stress voltages applied are |VGS| = 2.5V and |VDS| = 0V while project (funded by MICINN and ERDF). We would like to the measurement voltages are set to |VGS| = 0.6V and |VDS| = thank M. A. Lagos for his support in the design of the PCB. 0.1V. The measurements start 2ms after the stress is removed and 500 samples per second were acquired. The presented REFERENCES traces show discrete current steps as a consequence of charge [1] K.J. Kuhn et al, “Process technology variation,” IEEE Trans. on Electron detrapping from traps during the measurement time after the Devices, vol. 58, no. 8, pp. 2197-2208, Aug. 2011. application of overvoltage stress. Thanks to the use of the [2] M. J. M. Pelgrom, H. P. Tuinhout, and M. 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