Nanoscale Advances PAPER Does carrier velocity saturation help to enhance Cite this: Nanoscale Adv., 2020, 2, fmax in graphene field-effect transistors?† 4179 Pedro C. Feijoo, *a Francisco Pasadas, a Marlene Bonmann, b Muhammad Asad, b Xinxin Yang, b Andrey Generalov, c Andrei Vorobiev, b Luca Banszerus, d Christoph Stampfer, d Martin Otto, e Daniel Neumaier, e Jan Stake b and David Jiménez a It has been argued that current saturation in graphene field-effect transistors (GFETs) is needed to get optimal maximum oscillation frequency (fmax). This paper investigates whether velocity saturation can help to get better current saturation and if that correlates with enhanced fmax. We have fabricated 500 nm GFETs with high extrinsic fmax (37 GHz), and later simulated with a drift–diffusion model augmented with the relevant factors that influence carrier velocity, namely: short-channel electrostatics, saturation velocity effect, graphene/dielectric interface traps, and self-heating effects. Crucially, the model provides microscopic details of channel parameters such as carrier concentration, drift and saturation velocities, allowing us to correlate the observed macroscopic behavior with the local magnitudes. When biasing the GFET so all carriers in the channel are of the same sign resulting in highly concentrated unipolar channel, we find that the larger the drain bias is, both closer the carrier velocity to its saturation value and the higher the fmax are. However, the highest fmax can be achieved at biases where there exists a depletion of carriers near source or drain. In such a situation, the highest fmax is not found in the velocity saturation regime, but where carrier velocity is far below its saturated value and the Received 20th November 2019 Accepted 23rd July 2020 contribution of the diffusion mechanism to the current is comparable to the drift mechanism. The position and magnitude of the highest fmax depend on the carrier concentration and total velocity, which DOI: 10.1039/c9na00733d are interdependent and are also affected by the self-heating. Importantly, this effect was found to rsc.li/nanoscale-advances severely limit radio-frequency performance, reducing the highest fmax from 60 to 40 GHz. control, medicine etc.1 For the sustainable development, new Introduction materials with enhanced electronic properties are required. The development of new-generation radio-frequency (RF) elec- Graphene is considered as a promising channel material for RF tronics enables extending the range of advanced applications eld-effect transistors due to its intrinsically high charge carrier within the areas of communication, security imaging, quality mobility (up to 2  105 cm2 V1 s1) and saturation velocity (4  107 cm s1).2–6 However, RF performance of the graphene eld- a Universitat Autònoma de Barcelona, 08193 Cerdanyola del Vallès, Spain. E-mail: effect transistors (GFETs) was limited until recently by several PedroCarlos.Feijoo@uab.cat factors, for example, a relatively high drain conductance due to b Chalmers University of Technology, SE-41296 Gothenburg, Sweden zero bandgap, a high graphene/metal contact resistance and the c Aalto University, FI-00076 Helsinki, Finland extrinsic carrier scattering by charged defects.7–11 Continuous d 2nd Institute of Physics, RWTH Aachen University, 52074 Aachen, Germany efforts in the study of GFETs have resulted in an important improvement of the RF gures of merit (FoMs): the extrinsic e Advanced Microelectronic Center Aachen, AMO GmbH, 52074 Aachen, Germany † Electronic supplementary information (ESI) available: Section S1 details cutoff (transit) frequency (fT,x) and maximum frequency of fabrication and characterization of graphene devices used in this work. Then, Sections S2 and S3 present the mathematical modelling for the simulation of oscillation (fmax).12–17 This enhancement has been enabled, in the DC characteristics of GFETs and calculation of carrier velocity in graphene. particular, by the use of GFET models, which have allowed for Experimental and simulated transfer characteristics of GFETs are represented clarifying and overcoming RF performance limitations.18–27 in Section S4. Next, Section S5 includes the mathematical expressions used to Recently, values of fT,x ¼ 34 GHz and fmax ¼ 37 GHz for GFETs extract small-signal parameter and RF performance from the simulated DC with chemical vapor deposited graphene and a gate length (Lg) characteristics. Section S6 presents the measurements of the parasitic capacitances of the GFET. Section S7 shows the carrier concentration of 500 nm were reported by some of us.28 These RF FoMs distribution at biases where the magnitude of transconductance is maximized. outperform the ones obtained in other graphene-based tran- Section S8 delves deep into the effect of interface traps on GFET characteristics sistors with similar Lg, although higher values were achieved for and RF performance. Finally, Section S9 investigates the RF performance shorter Lg.29 Furthermore, these values of fT,x and fmax surpassed degradation caused by self-heating. See DOI: 10.1039/c9na00733d This journal is © The Royal Society of Chemistry 2020 Nanoscale Adv., 2020, 2, 4179–4186 | 4179 Nanoscale Advances Paper those of the best Si MOSFETs with similar gate lengths.30 The length of each ungated region of the channel was Lung ¼ achievement has been obtained by a combination of different 100 nm. The graphene layer was encapsulated between insu- improvements of the GFET design and fabrication process that lating layers of Al2O3 and SiO2 with thicknesses of tt ¼ 22 nm have resulted in high saturation velocity, low contact resistance, and tb ¼ 1 mm, respectively. The relatively thick SiO2 allows for and reduced extrinsic pad capacitances. reduction of the parasitic pad capacitances.28 High-resistivity A question that remains to be answered is whether operating (larger than 10 kU cm) silicon was used as substrate with the the GFET in a saturation velocity regime actually helps to get the aim of minimizing the substrate-related microwave loss in the highest fmax. The resolution to this problem needs a simulation GFET contact pads and transmission lines of the prospective tool that considers the factors that affect the current saturation, devices.31 Details on the GFET fabrication are included in namely, short-channel effects, velocity saturation effects, and Section S1 of the ESI.† self-heating effects (SHE). Our preliminary analysis indicated The GFET was simulated using the method described in ref. that these effects can be signicant when a GFET works at 24 and 25, which consists in solving self-consistently 2D Pois- relatively high drain elds, above 1 V mm1. In previous works, son's equation and 1D dri–diffusion transport equation. The a self-consistent simulator that accounted for short-channel dashed rectangle in Fig. 1(b) encloses the active area of the and velocity saturation effects was developed to investigate transistor and corresponds to the domain where the Poisson's the RF performance and scalability of GFETs.24,25 That simulator equation is solved. The simulator obtains the stationary distri- has been updated in the present work including the SHE with butions of graphene electrical parameters along the channel as two purposes: to study the DC and RF performance of the a function of the voltages applied to the gate-source and drain- prototype 500 nm GFET presented in ref. 28 and to explore source terminals (Vgs and Vds, respectively). Specically, it is whether there is still room for fmax improvement by exploiting possible to get the local parameters such as the charge carrier the saturation velocity regime. concentration for both electrons (n) and holes (p), the carrier This paper thoroughly studies the impact of drain current eld-dependent mobility (m), the separate currents and carrier saturation on RF performance as the interplay between carrier velocities driven by both dri (ndri) and diffusion mechanisms concentration (the gradient of which triggers the diffusion (ndiff), the Dirac energy (ED ¼ qj) and the quasi-fermi energy current) and velocity, which has only been slightly addressed (EF ¼ qV). The details of the simulator and the different carrier before.21 To investigate GFET performance, we follow an velocity denitions used in this work can be found in Sections approach that consists rstly in solving the dri–diffusion S2 and S3, respectively, of the ESI.† Key parameters as the at- equation self-consistently with the two-dimensional Poisson's band voltage (Vgs0), the residual charge carrier concentration equation to get the DC characteristics.24 This set of equations is, (r0), the low-eld mobility (mLF), and the contact resistance (Rc) in turn, coupled with the heat transfer equation that models the were extracted from measured low-Vds transfer curves (Ids–Vgs) SHE. Then RF performance is obtained from a quasi-static with holding time of 1 s at each bias point (see Section S4 of the small-signal model, whose parameters are extracted from line- ESI†). Aer that, we tted the measured output characteristics arization of the DC simulations.25 Such a methodology is thor- (Ids–Vds), which were obtained upon application of a holding oughly described in Methods. The combined analysis of DC and time of 30 s per measured point. That time is long enough for RF simulations allows us to assess the inuence of graphene the trapping/de-trapping processes to stabilize at high elds.32 electrical properties as the saturation velocity and low-eld The tting parameters are the interface trap density (Nit), the mobility, and other limiting factors as, for instance, the energy of optical phonons (ħU), whose emission limits carrier contact resistance, the interface traps and extrinsic capaci- dri velocity, and the effective thermal resistance (Rth). The tances. Thereby, we have obtained insights on the mechanisms latter will be discussed below. The model for the saturation dening the DC and RF performance of GFETs, which are dis- velocity nsat is given by:33 cussed in Results and discussion. Particularly, we have sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi addressed the question whether velocity saturation can help to 2U U2 1 nsat ðyÞ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1  2 r ðyÞ N (1) get better current saturation and if that correlates with p prsh ðyÞ 4pn F sh OP þ 1 enhanced fmax. Finally, the conclusions are drawn in the Conclusions section. Methods Device structure and description of the self-consistent simulator To investigate the bias dependence of RF performance and its relation with current saturation, we have numerically investi- gated the prototype GFET with high extrinsic fT,x and fmax described in ref. 28. Fig. 1 shows the GFET scanning electron microscope (SEM) image of the device and a schematic view of Fig. 1 (a) GFET SEM image and (b) schematic view (not drawn to scale) one of the two ngers. The GFET gate length and total gate of the gate region indicated in (a). The dashed rectangle encloses the width were Lg ¼ 500 nm and Wg ¼ 2  15 mm, respectively. The domain where the Poisson's equation is solved. 4180 | Nanoscale Adv., 2020, 2, 4179–4186 This journal is © The Royal Society of Chemistry 2020 Paper Nanoscale Advances 0 where Vds ¼ Vds  Ids Rc is the intrinsic drain-to-source voltage. This model considers an average temperature for the whole graphene sheet, so it neglects any local temperature deviation. It also neglects any temperature deviation at the proximities of the contacts, which could be a problem for graphene devices with Lg below 300 nm.35 Our previous measurements indicate that we can neglect the heat dissipated through the gate stack and at the proximity of the contacts,28 so the applied model is expected to work properly for the analyzed device. Using the values for mobility and carrier concentration ob- tained in this study we estimate the mean free path (MFP) by the Fig. 2 Carrier saturation velocity as a function of the carrier semiclassical model described in ref. 6 in the 10–100 nm range. concentration for different temperatures. The value of the optical Since the MFP is much shorter than the source-to-drain length phonon energy used has been ħU ¼ 0.10 eV. (Lg + 2Lung), it is conrmed that the dri–diffusion transport mechanism is appropriate for describing the electronic trans- port in the examined GFET. Transistors with shorter channel where T is the temperature, and rsh(y) ¼ n(y) + p(y) is the local lengths should be analyzed with ballistic or quantum models, carrier concentration at the position y in the channel. The which is beyond the scope of this work. phonon occupation NOP depends on temperature as: 1 Small-signal model of the GFET and derived RF performance NOP ¼ ! (2) ħU For the analysis of the RF performance, we consider the GFET as exp 1 kT a two-port network in common-source conguration. The device is characterized by its extrinsic admittance matrix Y. This matrix is calculated in two steps. First, the intrinsic admittance Eqn (1) and (2) show that saturation velocity strongly matrix Y0 is determined by the intrinsic small-signal equivalent depends on carrier concentration. Moreover, an increase in circuit model assuming quasi-static operation.36 Then the temperature slightly decreases nsat. These dependencies can be extrinsic Y matrix is obtained embedding the intrinsic GFET in seen in Fig. 2, where nsat has been represented for typical values a simplied extrinsic circuit of lumped elements, which of carrier concentration at several temperatures. consists of parasitic resistances at each of the three terminals We have used the following equation to model the eld- and parasitic capacitances at both the input and the output dependent mobility m(y) as a function of the local electric eld ports. Since tb [ tt, the back-gate capacitance is much smaller and saturation velocity, and thereby, also on rsh(y) and T: than the top-gate capacitance, so we can neglect the inuence of mLF the substrate capacitance in Y0 . Tunneling currents through any mðyÞ ¼  g io 1 (3) n h m   of the dielectrics are also neglected. LF vj g 1þ nsat ðyÞ  vy  Transconductance gm and output conductance gsd can be obtained from the derivatives of Ids respect to the intrinsic bias Here, a value of 1 has been used for the parameter g, consis- 0 0 voltages Vgs ¼ Vgs  Ids Rc =2 and Vds , respectively. Then, the tently with numerical studies of electronic transport in single small-signal capacitances are determined from the charges layer graphene relying on Monte Carlo simulations.34 associated to each of the terminals (Qi, with i ¼ s, d or g). They Unlike our previous works, we have included the SHE in the have been dened assuming a charge conserving Ward–Dut- self-consistent loop of the GFET simulator. This means that we ton's linear charge partition scheme.36 The transcapacitances assume that the temperature of the GFET rises because the heat Cgs, Cgd, Csd, Cdg are obtained as the derivative of charge at dissipated in graphene by the Joule effect nds difficulty to terminal i with respect to the intrinsic voltage at terminal j, 0 spread out of the device through the surrounding layers. By Cij ¼ dQi =dVj : For the calculation of the small-signal param- using the simplest thermal model, the temperature of the gra- eters, we assume that the temperature is constant at a given bias phene channel can be expressed as: point. A full description of the small-signal parameter and extrinsic admittance matrix calculation can be found in Section T  T0 ¼ RthPdis (4) S5 of the ESI.† Finally, the RF FoMs fT,x and fmax are extracted from the current gain and unilateral power gain that result from where T0 ¼ 300 K is the temperature of the heat sink, assumed the Y matrix.37 to be the environment temperature of the transistor and Rth is an effective thermal resistance that embraces all the paths through which the heat is dissipated. Pdis is the dissipated Results and discussion power in the GFET, which takes the following form:   First, we reproduced the experimental DC characteristics  0  Pdis ¼ Ids Vds  (5) following the methodology described in Methods. Fig. 3(a) shows the measured output characteristics of the GFET and This journal is © The Royal Society of Chemistry 2020 Nanoscale Adv., 2020, 2, 4179–4186 | 4181 Nanoscale Advances Paper Fig. 4 Measured (circles) and modelled (dotted lines) Y-parameters as a function of the frequency for a GFET biased at Vds ¼ 1.1 V and Vgs ¼ Fig. 3 (a) Measured (squares) and modelled (solid lines) DC output 0.5 V, corresponding to the highest measured fT,x ¼ 34 GHz and fmax ¼ characteristics of a GFET. Dashed lines correspond to the simulated 37 GHz. current neglecting SHE. (b) GFET temperature as a function of the drain bias due to self-heating. Next, we have benchmarked the small-signal model against the experimental Y-parameters. Fig. 4 shows the measured Y- their comparison with the simulations, where the parameters parameters in the 1–50 GHz range at Vds ¼ 1.1 V and Vgs ¼ used are presented in Table 1. The estimated Nit was found to 0.5 V, which correspond to the bias with the highest measured be lower than 1012 eV1 cm2, a value below which the fT,x ¼ 34 GHz and fmax ¼ 37 GHz. The four elements of the inuence of interface traps is negligible, as shown in Section complex admittance matrix are compared against our calcula- S8 of the ESI.† The best tting value of the Rc is 11 U, which tions. The intrinsic Y0 was directly extracted from the quasi- includes the metal/graphene contact resistance at both drain static small-signal model, while the values of gate series resis- and source together with the access resistances of the unga- tance Rg, the parasitic gate-to-source and drain-to-source ted graphene regions. Thus, the width specic contact capacitances, Cpgs and Cpds, respectively, were optimized to t resistivity results in RcWg/2 ¼ 165 U mm. The width specic the measured Y-parameters. Both series resistances at drain and metal/graphene contact resistivity of approximately 90 U mm, source, Rd and Rs, were assumed to be Rc/2. In addition to the evaluated applying the drain resistance model to the transfer good agreement between simulated and measured Y-parame- characteristic, agrees with the value of 95 U mm obtained by ters in the whole range of examined frequencies, Fig. S4 in the transfer length measurements (which exclude access resis- ESI† shows that the extracted values of Cpgs and Cpds, presented tance). From the tting done in Fig. 3(a), we obtained a value in Table 2, are similar to the ones measured from an open GFET of 2.7  104 K W1 for the Rth, which agrees with the order of structure (i.e. without the graphene layer), which conrms the magnitude of calculations based on the model by Pop validity of our approach. et al.,22,33 of around 3–4  104 K W1. Our simulator also Using the parasitic elements found in the previous step, we allowed us to calculate GFET temperature as a function of the analyzed the bias dependence of fT,x and fmax. The results are bias, shown in Fig. 3(b), and ranging between 300 and 1000 K. compared with measurements in Fig. 5, showing similar trends. The simulated temperatures are similar to the ones obtained A more detailed insight on the bias dependence of RF perfor- in previous works analyzing gate leakage current as mance can be obtained from the map of fmax shown in Fig. 6(a). a thermo–sensitive parameter. 38 A total of four maxima with fmax of 40 GHz are observed and labelled as A, B, C, and D, where A and C maxima occur at Table 1 Optimized parameters fitted from current–voltage characteristics Table 2 Values of the parasitic elements in the GFET extrinsic network Parameter Optimized value Parameter Optimized value Vgs0 2.2 V r0 2.9  1011 cm2 Rg 10 U mLF 2.0  103 cm2 V1 s1 Rs 5.5 U Rc 11 U Rd 5.5 U Nit <1012 eV1 cm2 Cpgs 4.6 fF ħU 0.10 eV Cpgs 7.6 fF Rth 2.7  104 K W1 4182 | Nanoscale Adv., 2020, 2, 4179–4186 This journal is © The Royal Society of Chemistry 2020 Paper Nanoscale Advances Fig. 5 Measured (squares) and modelled (solid lines) of (a) fT,x and (b) fmax as a function of the drain bias. Dashed lines represent fmax and fT,x switching off the self-heating effect. positive drain bias while B and D maxima at negative drain bias. Note that when gate voltage is equal to the Dirac voltage (i.e. Vgs ¼ VD z Vgs0 + Vds/2), transconductance gm changes its sign, which makes fmax 0. On top of that, for a given drain bias polarity, e.g. negative, the B maximum is located at Vgs < VD, Fig. 6 (a) Bias dependent fmax map. It presents four maxima labelled as which corresponds to a unipolar p-channel with the pinch-off A, B, C and D. Dashed lines represent the locus of considered drain bias close to the drain side, while at Vgs > VD, the D maximum points for fmax plot shown in (b) and |gm/gsd| plot in (c). Trans- corresponds to a unipolar n-channel with pinch-off close to the conductance, gm, and output conductance, gsd, are represented in (d) source side (see carrier distributions shown in Section S7 in the and (e), respectively. (f) and (g) show average drift velocity and satu- ESI†). Those maxima A, B, C and D are located at biases where ration velocity, respectively. Dashed lines correspond to the case where SHE have been switched off. there is a drop in the total carrier concentration close to the source or to the drain edges. It has been argued that the highest fmax needs current satu- ration in GFETs. To get the desired current saturation, it has than bias D, as can be seen in Fig. 6(c). GFETs tend to present been proposed that GFET operation close to the carrier velocity very low voltage gains due to the relatively large values of gsd41–44 saturation regime is helpful.17,21,39,40 Here we critically review but in this work we show that this is not an obstacle to reach this idea by means of Fig. 6, which helps to visualize the high power gain. For Vgs ¼ 1.1 V case, the B maximum is connection between the dri velocity and the small-signal reached at Vds ¼ 0.86 V, while for Vgs ¼ 1.0 V there is no an parameters (gm and gsd). Firstly, in Fig. 6(a) we have plotted absolute maximum of fmax, being fmax a monotonous function of the bias dependence of fmax, which displays four maxima. Vds, instead. Analyzing the average dri velocity in Fig. 6(f), we Notably, the bias locations of those maxima roughly coincide conrm the expectation that, far from the B maximum, the with the |gm| peaks (see Fig. S5 in the ESI†), so the |gm| maxima higher the dri velocity is (even approaching the saturation seem to be an adequate approximate rule to select the bias point velocity), the better fmax and the current saturation are, as if the intended FoM is fmax. However, there may be other options shown in Fig. 6(b) and (e), respectively. This behavior indeed to choose the bias point depending on the targeted FoM, for happens for biases far away from the Dirac voltage, where the instance, maximization of linearity, noise minimization, etc. channel behaves as unipolar. However, the largest fmax is For a deeper insight in Fig. 6(a), we analyzed fmax evolution at observed at biases near the crossover between unipolar and two different constant Vgs, the rst at Vgs ¼ 1.1 V passing bipolar behavior such as the B point, where it does not hold that through the maximum B (dashed blue line), and the second at the highest dri velocity, represented in Fig. 6(g), gives the Vgs ¼ 1.0 V (dashed green line) passing far away from the largest fmax, represented in Fig. 6(b). Fig. 6(d) and (e) show that maximum B. The resulting plot is shown in Fig. 6(b). We chose a high value of gm together with a relatively low value of gsd, i.e. bias B because it presents a higher voltage gain (ratio |gm/gsd|) a high voltage gain, is needed to reach the highest fmax possible. This journal is © The Royal Society of Chemistry 2020 Nanoscale Adv., 2020, 2, 4179–4186 | 4183 Nanoscale Advances Paper The bias point B and the bias corresponding to the maximum of |gm| slightly differ because fmax depends in a complex way not only on gm, but on gsd, the transcapacitances and the parasitic elements.45 On the other hand, fmax is not the highest possible when the GFET is operated far away from Dirac voltage, and this can be explained by the degraded gm and gsd, as shown in Fig. 6(d) and (e), respectively. The degradation of gm and gsd at bias E respect to the bias B is caused, in turn, by a decrease in the dri velocity because of the larger carrier concentration. The bias that maximizes RF performance is thus the result of a complex Fig. 8 Maximum fmax as a function of the Rth. It has been calculated interplay between carrier concentration and carrier velocity in within the 3rd quadrant of the coordinate plane (Vgs–VD, Vds) with |Vds| graphene, where self-heating plays a signicant role. < 1 V. Without SHE, fmax can reach 65 GHz. A local analysis of the carrier velocities along the channel at both biases E and B (Fig. 7) reveals more details on the central question of this paper, namely, if velocity saturation is needed a result of self-heating, which is triggered at |Vds| > 0.6 V. for the highest fmax. As there are two transport mechanisms at Additionally, Fig. 5–7 also show the SHE impact on the different play (dri and diffusion), we have introduced in S3 of the ESI,† parameters of the GFET. At biases near maximum values of fmax, as a matter of convenience, the denitions of dri, diffusion SHE are prominent and graphene temperature reaches 700 K. and total velocities that can be directly compared with the Importantly, Fig. 8 shows that SHE degrade the value of fmax saturation velocity. At the E bias, where the channel is unipolar from 65 to 40 GHz, mainly due to a decrease in vdri, which p-type, Fig. 7(d) shows that ndri dominates over ndiff and is reduces gm from 0.4 to 0.3 mS mm1 despite the larger ndri/nsat roughly 50% of nsat. The ratio ndri/nsat could be increased up to ratio. This way, it can be concluded that high temperatures limit 100% with a higher drain bias; for instance, it is 64% for Vds ¼ the RF performance of GFETs. Pop's model for thermal resis- 1.2 V, according to Fig. 6(f). However, at the B point, where the tance22,33 can estimate a reduction of up to 90% if the SiO2 was pinch-off is near the drain side, diffusion contribution is much substituted by a material like sapphire, which exhibits higher with ndiff/ndri around 40% near the drain, being ndri/nsat a thermal conductivity 30 times higher. This would mean an 45%, as can be seen in Fig. 7(b). Therefore, our results do not increase in fmax to almost the level of SHE-free GFETs, according support that operating in the regime of velocity saturation to Fig. 8 and assuming that all the power is dissipated through results in the highest fmax. the substrate. More details on the impact of SHE on RF To assess the impact of SHE, we have shown in Fig. 3(a) how performance can be found in Section S9 of the ESI.† SHE affects drain current, aer switching it on and off in the simulations. It can be observed that current saturation is Conclusions In this work we analyze the inuence of carrier velocity satu- ration on the RF performance of GFETs by means of a dri– diffusion self-consistent simulator. The model includes a number of effects dening the current saturation, namely, the two-dimensional electrostatics, saturation velocity effects, and self-heating effects, which are especially relevant at short channels and/or large drain bias. First, we optimized the model parameters to t the experimental DC characteristics of a prototype GFET. Then, the measured Y parameters were reproduced by tting the values of the parasitic capacitances and the gate series resistance using the GFET small-signal equivalent circuit. We simulated the bias dependence of the measured RF FoMs and we discussed the role played by satu- ration velocity in dening the highest fmax. For biases far from the Dirac voltage, where the channel is unipolar and highly concentrated, a higher dri velocity results in a larger fmax. However, the largest fmax are located at biases close to the onset Fig. 7 Distribution along the channel of relevant parameters at bias of bipolar conduction and far from the saturated velocity points labelled as B and E in Fig. 6(a). Solid lines correspond simulations regime. In that scenario the pinch-off point is close to either the with activated SHE (T ¼ 571 K at bias B and 723 K at bias E) and dashed source or drain edge and dri velocity there is no longer satu- lines to simulations switching off the SHE (T ¼ 300 K). (a) Electron and hole concentration at bias B and (c) at bias E. (b) Saturation velocity and rated. This is caused by the combined effects of carrier carrier velocity broken down into drift and diffusion velocities at bias B concentration and total velocity, which are interdependent. and (d) at bias E. Notably, we found a signicant degradation of fmax at high drain 4184 | Nanoscale Adv., 2020, 2, 4179–4186 This journal is © The Royal Society of Chemistry 2020 Paper Nanoscale Advances biases because of the self-heating. Based on these results, 7 K. D. Holland, N. Paydavosi, N. Neophytou, D. Kienle and further optimization of the GFET design for applications in M. Vaidyanathan, IEEE Trans. Nanotechnol., 2013, 12, 566– advanced RF electronics can be done by selecting the appro- 577. priate bias and reducing the effects of self-heating. 8 F. Giubileo and A. Di Bartolomeo, Prog. Surf. Sci., 2017, 92, 143–175. 9 Z.-Y. Ong and M. V Fischetti, Phys. Rev. B, 2012, 86, 121409. Authors contributions 10 S. Adam, E. H. Hwang, E. Rossi and S. Das Sarma, Solid State D. J., J. S. and A. V. conceived the study. P. C. F. conducted the Commun., 2009, 149, 1072–1079. research. F. P. and P. C. F. developed the theoretical models. C. 11 Z.-Y. Ong and M. V Fischetti, Phys. Rev. B, 2013, 88, 045405. S., L. B., A. V., A. G. and X. Y. developed the technology. X. Y. 12 H. Lyu, Q. Lu, J. Liu, X. Wu, J. Zhang, J. Li, J. Niu, Z. Yu, and M. B. contributed on device fabrication. A. V., M. A. and M. H. Wu and H. Qian, Sci. Rep., 2016, 6, 35717. B. characterized fabricated devices. D. J., J. S., A. V., M. A., M. B. 13 J. S. Moon, H.-C. Seo, M. Antcliffe, D. Le, C. McGuire, and P. C. F. contributed on the analysis of results. C. S. and L. B. A. Schmitz, L. O. Nyakiti, D. K. Gaskill, P. M. Campbell, grew high-quality chemical-vapour-deposited graphene. D. N. K.-M. Lee and P. Asbeck, IEEE Electron Device Lett., 2013, and M. O. developed advanced technology and carried out the 34, 465–467. transfer of graphene onto Si substrate. D. J., A. V., M. B. and P. 14 E. Guerriero, P. Pedrinazzi, A. Mansouri, O. Habibpour, C. F. wrote the manuscript. J. S., A. G. and F. P. provided feed- M. Winters, N. Rorsman, A. Behnam, E. A. Carrion, back on the manuscript dras. A. Pesquera, A. Centeno, A. Zurutuza, E. Pop, H. Zirath and R. Sordan, Sci. Rep., 2017, 7, 1–7. 15 I. Meric, C. R. Dean, S. J. Han, L. Wang, K. A. Jenkins, J. Hone Conflicts of interest and K. L. Shepard, Tech. Digest Int. Elect. Devices Meet., 2011, 2.1.1–2.1.4. There are no conicts to declare. 16 C. Yu, Z. Z. He, Q. B. Liu, X. B. Song, P. Xu, T. T. Han, J. Li, Z. H. Feng and S. J. Cai, IEEE Electron Device Lett., 2016, 37, Acknowledgements 684–687. 17 Z. Guo, R. Dong, P. S. Chakraborty, N. Lourenco, J. Palmer, This work was funded in part by the European Union's Horizon Y. Hu, M. Ruan, J. Hankinson, J. Kunc, J. D. Cressler, 2020 Research and Innovation Program under Grant Graphe- C. Berger and W. A. De Heer, Nano Lett., 2013, 13, 942–947. neCore2 785219 and No. GrapheneCore3 881603, in part by the 18 S. Rodriguez, S. Vaziri, A. Smith, S. Fregonese, M. Ostling, European Regional Development Funds (ERDR) allocated to the M. C. Lemme and A. Rusu, IEEE Trans. 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