This is the accepted version of the article: Nafria, Montserrat; Martin Martinez, Javier; Crespo Yepes, Albert; [et al.]. «Aging in CMOS RF linear power amplifiers : an experimental study». IEEE Transactions on Microwave Theory and Techniques, Vol. 69, Issue 2 (February 2021), art. 1453. DOI 10.1109/TMTT.2020.3041282 This version is available at https://ddd.uab.cat/record/248832 under the terms of the license > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Aging in CMOS RF Linear Power Amplifiers: An Experimental Study Xavier Aragones, Enrique Barajas, Albert Crespo-Yepes, Diego Mateo, Rosana Rodriguez, Javier Martin-Martinez, and Montserrat Nafria  that would minimize aging effects including select among Abstract— An extensive experimental analysis of the HCI and circuit topologies, which then can be verified with the aid of BTI aging effects on RF linear power amplifiers (PA) is presented software tools. in this paper. Two different 2.45 GHz PA topologies have been Aging is the result of different physical phenomena: Hot implemented in a CMOS 65 nm technology, one based on a classical common-source (CS) and choke inductor, another one Carrier Injection (HCI), Bias Temperature Instability (BTI), based on a complementary current-reuse (CR) circuit, both of Time-Dependent Dielectric Breakdown (TDDB), and Electro- them producing similar gain and output 1-dB compression point Migration (EM). Major reliability concerns in PA circuits are (P-1dB). These circuits have been stressed to produce accelerated related to TDDB and EM effects, because of their potential to aging degradation, by applying increasing supply (VDD) voltages, produce catastrophic failures derived from the large voltage and or increasing RF input powers (PIN). The degradation on the transistor parameters (threshold voltage and mobility), DC bias current spikes common in wireless transmitters. On the point (IDC current) and RF performance (gain, matching, contrary, HCI and BTI produce a progressive circuit compression point) have been simultaneously measured. This has degradation, and attract increasing interest. HCI was first allowed to observe how the reduced transistor degradation in CR observed in old 2 m technologies [4] and since then it has PA results in a higher robustness in its RF parameters, compared received considerable modeling efforts [5], [6]. HCI originates to CS PA circuit. The equivalent RMS voltages have been from high-energy carriers that become trapped in the oxide or proposed as an observable metric to assess the combined DC+RF stress in a PA circuit. This has been applied to a semi-analytical create interface states, thus associated to the existence of high model, thus providing comprehension of the link between the lateral electric fields. BTI phenomena also creates oxide and conditions under which a circuit is operated, the degradation of interface traps, but in this case because of the vertical electric the transistor parameters, and the effects on the DC current and fields in the oxide. MOS operating conditions (biasing) will RF performance. thus determine the dominance of HCI or BTI phenomena. One remarkable characteristic of BTI is that part of the device Index Terms— RF power amplifiers, IC reliability, aging in degradation is recovered when the stress is removed, while CMOS, BTI, HCI. another fraction becomes permanent [7], [8], [9]. The reported I. INTRODUCTION consequence of both HCI and BTI effects is an increase of the device threshold voltage VTH, and a decrease of the saturation D ESIGNERS of integrated circuits (IC) need to consider an increasing number of variability phenomena as technology scales down. In addition to the classical manufacturing current IDS [5], [10]. Previous works have evaluated experimentally the aging degradation of RF PA circuits, but some in the context of variability, circuit reliability requires to contemplate effects that switched operation (class-E) [11], [12], and only a few analyzed appear during circuit lifetime, such as the aging degradation [1]. linear PAs (class A or AB) [13], [14], [15]. In these works, In RF transceivers, the power amplifier (PA) circuit is aging is observed as a function of time but only in one or a few particularly prone to suffer aging effects, given the large stress situations. To obtain insight on how circuit aging is voltages appearing at device terminals. Introducing aging related to the DC bias and the RF signal, measurements for prediction in an IC design flow is now becoming possible with different DC and RF stress situations should be obtained. In specific models and the tools developed by major CAD vendors [16], [17] the HCI degradation on individual NMOS transistors [2], [3]. But besides simulation tools, circuit designers need a was experimentally measured under DC or combined DC+RF basic understanding of how circuit performance is degraded as stress, but then the effects on circuit RF metrics were estimated a consequence of transistor degradation, and how this by means of simulation, using fresh and aged transistor degradation is related to the circuit operating conditions. With parameters. All these experimental works have analyzed aging that understanding, designers can take the wise design decisions This research was funded by Spanish AEI –Agencia Estatal de A. Crespo-Yepes, R. Rodriguez, J. Martin-Martinez, and M. Nafria are with Investigación– and ERDF –UE–, grant numbers TEC2016-75151-C3-R and the Electronic Engineering Department, Universitat Autònoma de Barcelona, PID2019-103869RB-C3. 08193 Barcelona, Spain. X. Aragones, E. Barajas, and D. Mateo are with the Department of Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08034 Barcelona, Spain (e-mail: xavier.aragones@upc.es). > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 on the same conventional PA topology an NMOS loaded with broadband amplification up to 8 GHz. The first PA topology a choke inductor, while aging effects in other circuit solutions (named CR PA, Fig 1.a) is a self-biased complementary have only been evaluated through simulation analysis [18]. current-reuse amplifier. An off-chip resistance provides self- This work presents an experimental study to analyze the biasing, which sets the DC operating point. The second aging degradation specifically produced by HCI and BTI topology (named CS PA, Fig. 1.b) consists of a conventional phenomena, in linear RF PA circuits implemented in a 65 nm NMOS in common-source configuration loaded with a choke CMOS technology. We have designed a simple test circuit that inductor. In this configuration, the PA operating point is allows to observe individual transistor aging together with controlled externally through the gate voltage. The off-chip degradation of RF circuit metrics, in two representative basic resistive feedback and the VDD connection of the PMOS PA topologies. Results will show a drastic difference in terms transistor are disabled to create this CS configuration. On the of aging robustness between these two topologies. The analysis contrary, the off-chip choke inductor and the input DC bias performed demonstrates the reasons of that difference, and we connection are disabled in the CR configuration. An on-chip RC propose and validate a simple model to relate the combined DC feedback network guarantees broadband input and output +RF voltages to the degradation measured. This model allows impedance matching in both configurations [20]. to estimate transistors aging in other amplifier topologies, and An IC containing several instances of the above described consequently, the circuit performance degradation. This paper circuit has been manufactured in a CMOS 65 nm technology. A is an extension of [19][20], with significant extended photograph and a simplified layout of the test structure are experimental measurements, and deeper analysis, modeling and shown in Fig 2.a and Fig 2.b respectively. All transistors are discussion of the degradations observed. W/L = 180µm/60nm (45 fingers), and designed to stand DC The PA circuits, measurement set-up and aging experiments currents up to 100 mA. Both transistors, the RC network and are described in Section II. Section III focusses on the aging decoupling capacitors are integrated together with a 4GSG measured on the individual transistors, for each of the circuits structure for direct on-chip measurements in a probe station, and different stress conditions. The effect of that aging on the occupying an area of 700 µm  250 µm. DC bias point of the PAs is described in Section IV. An analysis Table I reports the characteristics of both PA circuit using a simple model allows to relate the DC current topologies in nominal conditions. Note in the CS configuration, degradation to the effects measured on the MOS parameters, the DC gate voltage is selected the same value as that produced and how these are related to the circuit operating conditions. in the CR configuration VIN = VOUT = 520 mV. Both topologies Finally, Section V shows the degradation observed on the RF provide similar performance in terms of gain, compression gain, matching, and compression point, and justifies the point and impedance matching at the frequency of 2.45 GHz, differences between both PA circuits. with the CR PA being more power-efficient, as otherwise II. EXPERIMENT DESCRIPTION expected. A. Power Amplifier Circuits An IC containing test circuits has been designed specifically for this experimentation, according to the following requirements: (i) circuits should provide reasonable performance as RF PA, including input and output matching for measurement with a Network Analyzer; (ii) all transistor terminals should be accessible, in order to allow individual transistor characterization; (iii) they should be flexible in terms of configurability or frequency of operation; and (iv) the circuit a) b) must stand large currents/voltages produced in stress Fig. 2. a) IC photograph of the configurable PA, terminals accessible with four GSG pad structures. b) Detail of the layout. conditions, necessary to accelerate aging effects. All these requisites led to the design of a single circuit, which allows to be configured as two different PA topologies. In both cases, the B. Measurement Set-up and Procedure resulting PAs are nominally operated as class-A, and provide A measurement-stress-measurement procedure has been followed to induce and observe aging degradation in both PA TABLE I NOMINAL PERFORMANCE OF THE PA CIRCUITS CR PA CS PA (NMOS+PMOS) (NMOS+Lchoke) VDD 1.2 V 1.2 V VIN_DC 520mV (=VOUT_DC) 520 mV IDC 7.3 mA 10.3 mA S21 @ 2.45GHz 10.3 dB 8.9 dB a) b) S11 @ 2.45GHz -8.5 dB -8.1 dB Fig. 1. Scheme of the (a) current-reuse –CR– and (b) common-source –CS– S22 @ 2.45GHz -10.4 dB -9.4 dB power amplifier circuits measured. Greyed region indicates the components P-1dB,OUT 5 dBm 5.3 dBm integrated in the IC, while the rest are implemented off-chip. PAE @ P-1dB 31.8% 22.9% > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 configurations: first, complete characterization of fresh –before a VDD voltage well above the nominal 1.2 V value, while the RF stress– amplifier and transistors is done; second, aging process stress consists in simultaneously applying a 2.45 GHz tone to is accelerated by operating the circuit in stressed conditions its input. Most of the measurements presented in this paper are during a given time; and finally, complete characterization of presented as two experiments, summarized in Table II. In the aged amplifier and transistors is repeated. This procedure Experiment 1, the same DC stress conditions are applied (same has been repeated for different stress conditions, each time VDD), while the input power of the RF stress component took starting with a new fresh circuit. The time elapsed between the values from a small -20 dBm value, to a significant +10 dBm. second and third steps in this measurement procedure was large This was the maximum power for which the circuits behaved as enough to guarantee that the recovery process in BTI was linear amplifiers and showed progressive increased completed, thus only the effects of the permanent BTI, and degradation. In Experiment 2, the same RF PIN = 6 dBm was those of HCI, were observed [8][9]. applied to all the samples, while the DC stress was changed by The experimental setup is shown in Fig. 3. A Vector Network applying different VDD supply voltages. Nominal stress time is Analyzer (VNA) is used to characterize the RF performance of 30 minutes in all these cases. Remark that changing VDD or PIN the circuit as well as to provide RF stress. Besides, a does not mean a continuous sweep during stress, but each stress Semiconductor device Parameter Analyzer (SPA) with Source situation (each combination of VDD and PIN values) was applied Monitor Units (SMU) is used for DC characterization (of both during 30 minutes, on a different fresh circuit sample. Besides circuit and transistors) as well as to provide circuit DC biasing these two reference experiments, a few other measurements and supply voltages during stress. Two external bias-T provide consisted of one-hour stress interrupted at regular time connection of the input and output terminals to the VNA and to intervals, which allowed intermediate measurements and obtain the external resistive feedback or SPA. The IC is unpackaged, IDC degradation trends as a function of time. and PA input and output are contacted with GSG coplanar During the different stress situations, the transistor junctions passive probes. The effect of all these cables and bias-T has are forced to strong voltage swings, resulting in electrical fields been de-embedded, both in the RF measurements and at DC that enable BTI and HCI aging mechanisms. Fig. 4 plots the VGS (including contact resistances). During measurements, the ICs and VDS voltages experienced by the transistors in both PA were glued to a thermally conductive support in order to circuits during Experiments 1 and 2, obtained from simulations minimize self-heating and allow temperature control. Further of the IC together with models of the external components. The details on the measurement setup and procedure can be found RMS of the total voltage is represented, since it captures the in [20]. contribution of both DC and RF components, and provides a better correlation to the observed degradation than the peak voltages. In fact, this metric is used in Section III as input to a semi-empirical model to predict transistor degradation. It must be noted that, while accelerated stress obviously also increases the drain current (up to 100 mA in the extreme cases), we have not observed a coherent correlation between the currents monitored and the measured degradations. As otherwise expected, simulations predict that transistors in the CR circuit are exposed to larger VGS voltages during the stress (VDD was increased above the nominal value during stress, while gate bias voltage in the CS circuit remained the Fig. 3. Diagram of the experimental set-up. The SPA provides both DC biasing during circuit operation and also allows DC characterization (of PA circuit and individual transistors). The VNA provides RF power during stress, and also is required for characterization of RF circuit performance. C. Description of the Stress Experiments Different combinations of DC and RF stress have been applied to the PA circuits. The DC stress consists of supplying TABLE II SUMMARY OF AGING EXPERIMENTS PERFORMED ON THE PA CIRCUITS Experiment 1 Experiment 2 Aging dependence on Aging dependence on the RF component the DC component VDD = 2.8 V VDD  {2.0, 2.8} V CR PA topology RF PIN  {-20, +10} dBm RF PIN = +6 dBm VDD = 2.2 V VDD  {1.8, 2.4} V CS PA topology Fig. 4. Expected VGS and VDS voltages experienced by the transistors in both RF PIN  {-20, +10} dBm RF PIN = +6 dBm PA circuits during Experiments 1 and 2, obtained from circuit simulations. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 same). On the contrary, the NMOS transistor in the CS PA circuit will be exposed to larger VDS voltages than the transistors in the CR PA circuit. Therefore, it is expected that both PA circuits, although producing similar overall performance as shown in Table I, will experience important operation differences that will trigger differently the BTI and HCI effects. III. MEASUREMENTS OF AGING IN MOSFETS A. NMOS and PMOS Degradation with DC and RF Stress As a consequence of the stress applied, transistor characteristics are progressively degraded. For illustrative purposes, Fig. 5 depicts the ID(VGS) curves of the NMOS and PMOS transistors of the CR PA circuit, measured after several interruptions in a one-hour stress, in this case for a DC stress condition of VDD = 3 V and RF input power PIN = 6 dBm. Aging modifies the DC transistor characteristics, shifting the curves to Fig. 6. Extracted variation of VTH –a) and c)– and mobility  –b) and d)– after higher voltages –VTH increase– and reducing the slope 30 min. of stress in Experiments 1 and 2. Comparison between degradation of –mobility decrease–. A first observation is that, although the the NMOS (solid) vs. that of the PMOS (hollow) in the CR PA topology. stress intervals are increased following a potential law, curves are approximately equally spaced. This means aging source and drain voltage drop in the measurement setup. degradation is dominantly produced in the first instants of 0  Cox W 2 VDS  VGS  VTH VDS  circuit operation, which is consistent with classical models [4]. ID  (1)  A second observation is that, although both transistors are 1   VGS  VTH  L  2  stressed with similar voltages –in fact, larger VGS and VDS in the Fig. 6 plots the variation observed in these parameters, for PMOS, see Fig. 4–, the effects on the NMOS transistor are the NMOS and PMOS transistors of the CR PA, after significantly more important that those suffered by the PMOS Experiments 1 and 2. Results show that the degradations of both device. VTH and  parameters of the NMOS are significantly larger than those of the PMOS, as expected from observation of Fig. 5. Most interestingly, it can be seen how a large DC stress alone (VDD = 2.8 V but small PIN) or large RF stress alone (PIN = 6 dBm but small VDD) do not produce significant degradation of the transistor parameters. On the contrary, degradation shows only after the combination of DC+RF stress. Also the amount of degradation produced by changing VDD or PIN is similar. Fig. 5. Degradation of the characterisc ID(VGS) curves @ VDS = 50 mV, of the These observations denote similar relevance of the DC and RF NMOS and PMOS transistors of the CR PA, after increasing stress times. Stress components in the aging degradation, in agreement with some conditions are VDD = 3.0 V together with a RF 2.45 GHz tone of PIN = 6 dBm. previous simulation [24] and experimental [13] works. While BTI degradation is conventionally more important in B. NMOS Degradation vs. PA Circuit PMOS transistors (NBTI), HCI produces stronger degradation The same experiments done on the CR PA topology (aging in NMOS [1]. This difference related to HCI is mainly vs. RF stress component and aging vs. DC stress component) attributed to the shorter mean-free path of holes in PMOS are now repeated for the second CS PA configuration. Note in transistors [4], which can be related to the different carrier this case the single NMOS transistor sees the VDD voltage mobility. The lower HCI degradation of PMOS short-channel directly applied to its drain terminal, thus smaller DC stress transistors compared to NMOS has been experimentally values are selected for this topology (see Table II). The power of the input tone producing the RF stress component is the same verified under constant DC stress [22]. Our observations then in both circuit topologies, for each of the experiments. suggest that HCI is probably the dominant degradation Fig. 7 compares the degradation observed, for each stress mechanism produced in our circuits, which will be later combination, on the VTH and mobility of the NMOS transistor endorsed with other observation. in each of the circuit topologies. Remember this NMOS device In order to evaluate quantitatively the MOS transistor is physically identical in both PA circuits. It can be observed degradation under different stress conditions, threshold voltage how, for the same applied stress, the NMOS transistor in the CS VTH and mobility 0 have been extracted from the above ID(VGS) PA suffers significant stronger degradation than in the CR PA. curves in the ohmic region. A least-squares algorithm was used Compare for example the degradation after VDD = 2.4 V and PIN to determine the VTH and 0 values that minimize the error = +6 dBm (Fig. 7.c and 7.d): the NMOS in the CS PA suffers between measurements and the simple MOS model in the triode degradation of VTH and  of 10.3% and 54.4% respectively, region (1) with mobility degradation [23], after deembedding which reduce to 3.9% and 8.9% for the NMOS in the CR PA > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 Fig. 8. VTH degradation measured (X-axis) vs. model prediction (Y-axis). Measurements include Experiments 1 and 2 in both the CR and CS PA circuits (values in Fig.7), and also other stress situations for different VIN_DC and VDD values in the CS circuit. Model prediction as of Eq. (4), where voltages are RMS values obtained from circuit simulations (Fig. 4). to account for the signal stress component [17], but this Fig. 7. Extracted variation of VTH –a) and c)– and mobility  –b) and d)– after prevents usage for hand calculations. As a compromise between 30 min. of stress in Experiments 1 and 2. Comparison between degradation of accuracy and simplicity, we propose to use the RMS 1 VGS and the NMOS in the CR PA topology (solid) vs. that of the NMOS in the CS PA VDS voltages in the transistor as a metric that captures the topology (hollow). combined DC and RF stress producing aging degradation. circuit. Even with negligible RF signal (PIN = –20 dBm), the These equivalent voltages can be easily obtained from a simple NMOS in the CS PA is significantly degraded (degradation of transient simulation of the circuits. Then, a simple and intuitive VTH and  of 3.9% and 25.8% respectively) while the NMOS in prediction of the threshold voltage degradation can be obtained the CR PA suffers practically no degradation. from simple exponential dependences on RMS VGS and VDS voltages, C. Modeling Transistor Degradation Produced with DC + 1VGS ,rms  2VDS ,rms RF Stress VTH  1  e  t n1 (4) Nowadays, most PDKs (Process Design Kits) for nanometer where 1, 1 and 2 are technology-dependent parameters. An technologies include MOS parameters for complex aging equivalent expression is proposed to estimate the degradation models. Circuit designers then can use specific simulation tools of the µ·Cox parameter: [25] to predict the performance of a circuit after years of  3VGS ,rms  4VDS ,rms operation, when degraded as a consequence of HCI and BTI   Cox   2  e  t n2 (5) effects. Although these complex models can provide accuracy, The aging degradation observed in the NMOS transistors in simple models are preferred to obtain fast, handy estimations, our circuits has been compared against the RMS voltage but most important, to provide intuitive relationships helpful to dependence expressed in (4)(5). Simulation of the CR and CS the circuit designer. We propose in this section to validate a PA circuits in the different stress situations in Experiments 1 simple procedure to relate DC and RF operating conditions to and 2 allowed to obtain the RMS values of the VGS and VDS the circuit degradation observed. voltages in the transistor terminals, represented in Fig. 4. Then Analytical models to predict HCI and BTI degradation were derived in [6], [9], which were later simplified to the compact we have empirically extracted values for i and i·tn coefficients expressions (2)(3), consisting of a potential time law multiplied (with t = 1800 s) that would best fit the predictions in (4)(5) to by exponential dependences on the lateral and vertical electrical the measured degradations. Fig. 8 compares the measured fields [1]: degradation on the threshold voltage (Fig. 7a and 7c) against  HCI 2   HCI 1Eox VTH , HCI  e e Elat t nHCI (2) Ea   BTI 1VGS kBT nBTIp VTH ,BTI , permanent  e e t (3) The exponent in the time-potential law is a constant, as discussed in [4]. These expressions were further simplified in [18] as simple exponential dependences on the VGS and VDS applied voltages. These resulting models are simple enough for handy estimation, but were only validated in DC situations. Ignoring the RF stress contribution to aging degradation is not an option outside the small-signal regime, as evident from the Fig. 9. µ·Cox degradation measured (X-axis) vs. model prediction (Y-axis). measurements in our PA circuits. Time-integration can be used Measurements include Experiments 1 and 2 in both the CR and CS PA circuits (values in Fig.7), and also other stress situations for different VIN_DC and VDD values in the CS circuit. Model prediction as of Eq. (5), where voltages are 1 RMS of total voltage including both DC and AC components. RMS values obtained from circuit simulations (Fig. 4). > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 6 the model prediction (4). The plot also includes other stress combinations (VBIAS and VDD values) different to those of the VDD and PIN sweeps. A strong correlation between model predictions and experimental results is observed, validating the method proposed to produce first-hand estimations. The process has been repeated to fit the measured degradation of mobility (Fig. 7b and 7d) to expression (5) (assume Cox remains constant). Fig. 9 shows how the prediction based on simulated RMS voltage now shows even better correlation to the measured aging, despite the situations analyzed include two different PA circuits, at different bias points, different DC and RF stress conditions, with the same Fig. 11. Degradation of the DC bias point in the CR PA as a function of the technology-dependent parameters. stress time, for different DC stress conditions and PIN = 6 dBm. Note the Fig. 8 and Fig. 9 then validate the relationship between degradations in Fig. 7 correspond to an stress time of 1800 s in this plot. equivalent RMS voltages in the transistor terminals, and the progressive degradation produced as a consequence of HCI and the NMOS and PMOS transistor degradations in this circuit. BTI effects. Note this is in contrast to other reliability For a DC analysis, the CR PA can be viewed as a voltage degradation issues in PAs, which may be triggered by divider. The consequence of the aging degradation is an occasional transient events. increase in the drain-source channel resistance of both transistors, but since the degradation in the PMOS device is IV. BIAS POINT SENSITIVITY TO MOSFET AGING smaller than that of the NMOS (Fig. 6), the result is a small increase in the DC intermediate voltage. A. DC Circuit Degradation While all the measurement results presented so far are The degradations in the threshold voltage and mobility of obtained after a 30-minute stress, it is interesting to the MOS transistors in both PA configurations produce a experimentally observe how the degradation evolves after modification of the bias point in these circuits, which will increasing stress times. To obtain this time dependence, the ultimately impact their RF response. This section presents the stress applied to each circuit sample was stopped at regular measurements of the degradation suffered in the DC bias point intervals, and intermediate MOSFET and circuit of the CR and CS PA circuits, for each of the experiments characterizations were done at those instants. These time described in Section II.B. For the CR PA configuration, which measurements have been done for only one of the experiments is self-biased, both the DC current IDC, and the DC voltage in Table II: VDD dependence (Experiment 2). The bias point (IDC VINV = VIN_DC = VOUT_DC are measured, while for the CS PA current) degradation on the CR PA circuit observed as a configuration, where DC voltages are set externally, only the function of the stress time is plotted in Fig. 11. For a better IDC current is evaluated. Nominal values for these parameters reading, time is plotted in a log scale, since most degradation is before aging is produced are detailed in Table I. produced in the first minutes. Note for example how, when The degradations measured after 30 minutes of accelerated stressed with VDD = 3.0 V, one minute is enough to produce a stress for each of the experiments are plotted in Fig. 10. It can 10% degradation in the IDC current of the CR PA. Fig. 11 shows be observed how the dependences with the DC (VDD) or RF a power-law time degradation of IDC, with time exponent (PIN) stress components follow qualitatively those of the MOS n  0.43. Note this is consistent with the models for the VTH parameters in Fig. 7. In particular, the strong difference in aging degradation produced by HCI and permanent BTI aging degradation between the two circuit topologies becomes phenomena [4], [6], [9], as well as the prediction proposed in evident now. For example, after being stressed with VDD = 2.4 V (4)(5). and PIN = 6 dBm, the IDC current in the CS PA suffers a 65% B. Predicting DC Circuit Degradation Produced by NMOS decrease, while the CR PA stressed in the same conditions Aging during the same time only experiences a 12% degradation. Besides being more robust in terms of IDC decrease, the CR The predictions of VTH and mobility degradation offered by PA experiences a very small variation in the DC input-output Eq. (4) and (5) can be used to predict analytically the impact on voltage. This is a consequence of the complementary effects of the bias point in simple circuits. Furthermore, this can provide insight into how transistor aging translates into circuit degradation. Drain current for an NMOS in the saturation region can be approximated as VGS  VTH  1  V 2  0 C ox W (6) I DC   DS  2 L 1   VGS  VTH  where λ is the channel length modulation factor, and θ models the mobility degradation produced with strong electrical fields Fig. 10. Degradation of the DC bias point in the CR and CS amplifers after 30 min. of accelerated stress in the experiments detailed in Table II. Decrease of [23]. Assuming moderate aging degradations of VTH and 0, and the DC current is plot, and also the variation of DC voltage in the CR circuit. neglecting the possible degradations suffered by Cox,  and  > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 7 parameters, the variation produced in IDC as a consequence of Eq. (5) proposes that it is possible to estimate the mobility aging can be approximated as degradation from a linear combination of RMS drain and gate voltages during the stress. From the experimental I DC I (7) I DC  0  DC VTH measurements in the 65 nm transistors, the linear coefficients  0 VTH 3 = 1.07 and 4 = 1.79 were extracted. Although these values Inserting (6) into (7), the relative degradation of the drain point to a higher impact of the VDS voltages on the transistor current can be expressed in function of the relative variations of degradation, drain voltage is not necessarily the reason of the the threshold voltage and mobility as: trends observed in the different experiments in this work. For example, observing the RMS voltages in Fig. 4 for the CS PA I DC  0  3  VTH VTH  VTH circuit, VDS,rms increases only moderately after increasing PIN,     I DC  0 1   VGS  VTH  1   VGS  VTH   VGS  VTH   VTH since the PA enters into compression (peak VDS voltages (8) saturate, in fact). On the contrary, the VGS,rms voltage almost doubled when increasing PIN from -20 to +10 dBm. In contrast, Observe how this expression can be evaluated from the the degradation of the CS PA observed in Experiment 2 nominal models parameters in the saturation region, and from (increased VDD values) is fully related to the increase of VDS,rms the VTH and mobility degradations estimated from (4)(5). We voltage, as far as the gate voltage remains unchanged. The have produced this evaluation for the CS PA circuit, and models proposed thus allow to establish comparisons between compared it against the measured IDC degradation measured different operating conditions accounting for both the DC and after 30 min. of stress, represented in Fig. 10. The comparison AC (RF) contributions. But also, allow to compare the expected of the prediction using (4)(5)(8) against measurements is shown aged performance of different circuit solutions. Applied to the Fig. 12, for each of the Experiments 1 and 2, and also for other circuits measured in this work, the model explains how the arbitrary stress situations (different VIN_DC and VDD). It can be lower VDS voltages in the MOS transistors of the CR PA observed how the simple model prediction provides a useful produce a lower degradation of this circuit, compared to the CS estimation of the combined effect of a DC and RF stress on the PA. This conclusion can be extended to other similar circuit aging degradation of the PA circuit. solutions (e.g. cascode [27]). Besides quantitative estimation, Eq. (8) can be used to provide an intuitive understanding of the relationship between V. AGING DEGRADATION OF PA RF PERFORMANCE DC bias current and transistor degradation. According to the first term in this equation, mobility degradation is directly The experimental study of aging degradation experienced by translated to degradation of IDC current. On the contrary, the the CR and CS PA circuits has been completed by variation of the threshold voltage has a lesser impact on IDC, characterizing their RF response. S-parameters have been because the VTH degradation is small compared to that of the measured for each of the experiments, before and after stress, mobility (Fig. 7), but also because of the two subtracted terms together with the 1-dB compression point. in Eq. (8). In the predictions represented in Fig. 12, the A. Aging effects on the Gain contribution of the VTH term in Eq. (8) was always below 10% of the total result. Therefore, mobility degradation is the In class-A operation, the reduction of the DC current dominant contributor to the DC current degradation in these observed in Section IV directly degrades the transistors experiments, and this explains the similarity between the IDC transconductance gm, and thus the amplification provided by the and µ degradations in the CS PA (Fig.7.b compared to Fig.10.a; CR and CS PA circuits. Fig. 13 plots the variation observed in Fig.7.d compared to Fig.10.b). While many works in the the small-signal gain parameter S21, measured at 2.45 GHz literature focus on modeling only the VTH degradation as a frequency, after each of the experiments in Table II. As consequence of aging phenomena [6], [26], the above expected, the gain degradation as a function of the DC and RF observation highlights the need to observe and model the effects stresses (VDD and PIN, respectively) follows the general trends on the mobility [10]. observed for the IDC current variations in Fig. 10. But a close comparison of Fig. 10 and Fig. 13 reveals that the degradation of the CR PA circuit, compared to that of the CS PA, is even lower when observed in terms of gain. To get more insight in this comparison, the relative degradation of S21 parameter (now in linear units) is plotted against the relative degradation of the Fig. 12. DC current degradation in the CS PA, measurements (X-axis) vs. model prediction (Y-axis). Measurements include Experiments 1 and 2 (values in Fig.7), and also other stress situations for different VIN_DC and VDD values. Model prediction as of Eq. (7), where VTH and µ degradations have been Fig. 13. Degradation of the S21 gain parameter at 2.45 GHz, in the CR and CS estimated using Eq. (3) and (4). amplifers after 30 min. of accelerated stress in the experiments in Table II. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 8 B. Aging effects on matching In the CR and CS PA circuits designed in this work, broadband impedance matching is obtained with the addition of shunt-feedback (RF in Fig. 1). Therefore, from basic circuit analysis, gain degradation is expected to affect severely the matching parameters. Fig. 15 shows the measured value of the S11 parameter at 2.45 GHz, after the different stress experiments. As predicted, the shunt-feedback solution degrades matching following a close correlation to the gain degradation in Fig. 13. Similar trends were obtained for the S22 parameter. This particular experiment illustrates how an Fig. 14. Degradation of the S21 gain parameter at 2.45 GHz, in the CR and CS amplifier with acceptable matching (see nominal values in amplifers, related to the DC current degradation after 30 min of accelerated Table I) can turn into a mismatched amplifier as a consequence stress in the experiments detailed in Table II. Points are the experimental measurements (Fig. 10 and Fig. 13), while lines are interpolated linear trend of aging phenomena. laws for each amplifier. C. Effect of the circuit temperature DC current, for all the experiments represented in Fig. 10 and Maximum output power delivered by the test PA circuits is 13. The resulting plot is shown in Fig. 14. It can be observed slightly beyond the 5 dBm compression point, and this is a how linear relationships between DC current variations and relatively low power compared to high-end 2.45 GHz PAs gain variations are observed, irrespective of the type of stress delivering 30 dBm. While a few dBm POUT is reasonable in (DC or RF) that has produced that degradation. But remarkably, low-end PA’s, a differential aspect as power is increased is the the different slopes indicate that the bias current degradation temperature increase produced by self-heating effects. In our affects more importantly the gain in the CS PA, than the gain of experimental set-up, self-heating effects were minimized since the CR PA. The gain in the CR PA is contributed by the small- the ICs were glued with conductive epoxy to a metal support signal transconductances of both NMOS and PMOS (gmN and directly attached to the chuck, thus providing excellent thermal gmP, respectively), while the gain in the CS depends only on the dissipation. Still, we want to investigate how the gain NMOS. As observed in Section III.A, the degradation of the degradation is affected when the stress is produced at increasing PMOS transistor is smaller than that of the NMOS, for a given temperatures. For that purpose, we used a thermo-chuck to stress situation. Therefore, degradation of gmP is lower than that apply increasing temperatures to the circuits. The same stress of gmN. The circuit with a gain contributed by both gmN and gmP was applied to both PA configurations, VDD = 2.8 V and PIN = 6 will be thus less sensitive to degradation of the DC current than dBm, with interruptions after 6, 30 and 60 minutes. The gain a circuit where the gain depends entirely on gmN. This explains performance of the circuits was characterized after each of these the different sensitivity of the gain to DC current variation in interruptions. the CR and CS PAs, shown in Fig. 14. The measured evolution of the gain after increasing stress The above discussion allows to conclude that the CR PA times is plot in Fig. 16, for the different temperatures. A first, topology is more robust against aging, compared to a more expected observation is that at time zero, gain reduces as a conventional CS topology, because of a double reason. On one consequence of the temperature increase. As observed in [16], side, for the same DC bias and RF input, the current-reuse threshold voltage decreases and mobility increases with topology produces lower VDSrms voltages in the transistors, temperature. In voltage-mode biased amplifiers, this produces which result in lower transistor aging, and thus lower complementary effects on the DC current. Still, because of the degradation of the DC current. But besides that, the gain of CR strong effect on the mobility, the result is a gain reduction. This circuit happens to be less sensitive to DC current variations than degradation is lower in the CR PA topology, because of the the gain of the CS topologies. As a result of this, the effects of lower impact on the PMOS and its reduced dependence on the aging on the amplification (and thus output power) in a CR PA DC current, as discussed in Section V.A. are largely smaller than in a CS topology. Lifetime of these After applying accelerated stress, gain degradation is circuits extrapolated to nominal supply (VDD = 1.2 V) was produced, stronger in the CS circuit in coherence with estimated in [19]: while in the CS PA a gain degradation of 3dB measurements in Fig. 13. Interestingly enough, the initial would be produced after approximately only 3 yr, it would take differences observed at increasing temperatures tend to vanish in the order of 100 yr in the CR PA. Fig. 16. S21 time evolution, measured at nominal VDD = 1.2 V, after accelerated Fig. 15. S11 at 2.45 GHz, in the CR and CS amplifers after 30 min. of stress at increasing temperatures. Measurements on the CS PA topology (a) and accelerated stress in the experiments in Table II. on the CR PA (b) circuit topologies. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 9 as stress time increases, leading to approximately the same degraded gain values after one hour of stress. Results thus indicate that no significant differences on the RF gain performance resulting after aging degradation are expected by operating our circuits at higher temperatures. D. Aging effects on the Compression Point While the experiments above have evidenced the better robustness of the CR PA in terms of gain and matching degradation, its PMOS+NMOS structure may look prone to suffer linearity degradation. Contrary to this intuition, the nominal (fresh) output-referred compression point of this circuit is only slightly (0.3 dB) worse than that of the CS PA. We have measured how this compression in the CR PA is degraded as a consequence of the aging produced after each of the experiments in Table II. Results in Fig. 17 show that, while aging degrades the output-referred compression point, the degradation produced is moderate, 0.6 dB in the worst case. Note that, since the S21 degradation is stronger (more than 1 dB, in the worst case), the input-referred compression point is actually increased (the PA can allow more input power to reach compression). The variations experienced in P-1dB are anyhow Fig. 18. Degradation of S21 (top) and P-1dB,OUT (bottom) at 2.45 GHz in the CR small, and show that the CR PA solution is not disadvantageous PA, produced by RF stress at different frequencies (symbols). Stress condition in this respect. was VDD = 2.8 V and PIN=6 dBm. Superposed (continous line) is the frequency response of the PA before the stress. In order to improve robustness against aging variability, self-healing techniques have been proposed in CS-based PA as the frequency response of the PA circuit. While the same VDD topologies in order to adaptively adjust the transistor bias after and RF input power were applied at all frequencies, the RF sensing the output power [28], [29]. Being a self-biased output swings decrease as the PA gain decreases at high amplifier, such approach cannot be directly applied to the CR frequencies, thus producing less degradation. PA. Instead, gain loss should be compensated by increasing the power coming from pre-amplification stages, namely PIN in our VI. CONCLUSION measured PA circuit. Results in Fig. 17 show that this a feasible approach, as far as output compression remains slightly affected The results of an experimental study to observe and by the aging degradation. comprehend the aging produced in linear RF PA circuits have been presented. A circuit has been designed in a 65 nm CMOS E. Aging dependence on the frequency of the RF stress technology, that allows to be externally configured as two Since one of the observations in this work is the importance different representative PA topologies, one based on current- of the RF stress component, we have finally evaluated the aging reuse, and one common-source loaded with choke inductor. degradation as a function of the frequency of this RF stress Both topologies produce similar PA performance at 2.45 GHz. component. The analysis has been done only in the CR PA, Aging effects produced by HCI and BTI have been measured at stressed at VDD = 2.8 V and PIN = +6 dBm during 30 min. The both transistor and circuit level after different experiments of degradation of the gain parameter (S21) and output-referred accelerated stress. Experiments have evidenced the importance compression point (P-1dB,OUT) measured at the PA operation of the RF signal on the PA aging: variations produced after frequency of 2.45 GHz is plotted in Fig. 18, in both cases increasing VDD voltage well above the nominal 1.2 V value were together with the frequency response of the PA (before stress). negligible if no RF signal was applied, while important Results show that the degradation effects decrease as frequency degradation was observed after adding a RF signal component. of the RF stress is increased, following roughly the same trend Measurements have shown how aging produces important degradation of MOS mobility and threshold voltage parameters, being the mobility the most affected. MOSFET degradation results in reduction of the DC current in the PA circuit, and simple models have allowed to relate this DC current variation dominantly to the mobility degradation of the NMOS transistors. We have proposed the equivalent RMS voltage in transistor terminals as a compact and intuitive metric to relate combined DC+RF stress to the aging degradation, which has been validated against experimentation. By using a simple compact model, this has allowed to identify the smaller Fig. 17. Output-referred (back squares) and Input-referred (red circles) 1-dB equivalent voltage at the drain terminals of the transistors in a compression point in the CR amplifier after 30 min. of accelerated stress in the CR PA topology as the main responsible for its fairly better experiments in Table II. Middle curve (cross symbols) plots the degradation of robustness against aging, compared to a classical CS solution. the 1dB compression. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 10 As a consequence of the smaller bias point degradation, the stresses," Solid-State Circuits, IEEE Journal of, vol.47, no.5, pp.1075- 1083, May 2012. aging impact of the PA gain at 2.45 GHz is dramatically smaller [18] S. Mahato and G. Gielen, "Impact of transistor aging on RF low noise in a CR circuit than in an equivalent implementation based on amplifier performance of 28nm technology: Reliability assessment," a CS topology. Besides, it has been observed that PMOS Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International transistors suffer significantly smaller degradation than NMOS Conference on, Abu Dhabi, 2013, pp. 413-416. ones, which also contributes to the smaller degradation of the [19] X. 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