This is the accepted version of the article:
Diaz-Fortuny, Javier; Saraza-Canflanca, Pablo; Rodriguez, Rosana; [et al.].
«Statistical threshold voltage shifts caused by BTI and HCI at nominal and
accelerated conditions». Solid-State Electronics, Vol. 185 (November 2021), art.
108037. DOI 10.1016/j.sse.2021.108037


This version is available at https://ddd.uab.cat/record/249447

under the terms of the                license
      Statistical threshold voltage shifts caused by BTI
       and HCI at nominal and accelerated conditions
J. Diaz-Fortuny1*, Pablo Saraza-Canflanca2, Rosana Rodriguez1, Javier Martin-Martinez1, Rafael Castro-Lopez2, Elisenda Roca2,
                                       Francisco V. Fernandez2 and Montserrat Nafria1
              1UniversitatAutònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain
                        2Instituto
                                de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain
  E-mail address of corresponding author: javier.diazfortuny@imec.be *currently affiliated with imec, Kapeldreef 75, 3001 Leuven, Belgium

Abstract— In nowadays deeply scaled CMOS technologies,                  techniques are based on the application of serialized
time-zero and time-dependent variability effects have                   measurement-stress-measurement (MSM) sequences. The MSM
become important concerns for analog and digital circuit                characterization technique consists of an initial measurement
design. For instance, transistor parameter shifts caused by             phase, in which the “fresh” characteristics of the device are
Bias Temperature Instability and Hot-Carrier Injection                  measured, a stress phase, that accelerates the device degradation
phenomena can lead to progressive deviations of the circuit             by means of the application of an overvoltage to the device
performance or even to its catastrophic failure. In this                terminals, and another measurement phase, where the effects of
scenario, and to understand the effects of these variability            the induced aging can be measured in reasonable testing times.
                                                                        In order to obtain statistically-relevant information, a statistical
sources, an extensive and accurate device characterization
                                                                        aging test, with hundreds or thousands of transistors under the
under several test conditions has become an unavoidable
                                                                        same stress and measurement conditions, must be performed.
step towards trustworthy implementing the stochastic                    Typically, wafer-level device characterization implies that
reliability models and simulation tools needed to achieve               devices are tested one by one leading to a continuous experiment
reliable integrated circuits. In this paper, the statistical            of days or months. In our work, we use our previously designed
distributions of threshold voltage shifts in nanometric                 65-nm array-based IC [10] in combination with a custom-
CMOS transistors will be studied at nominal and                         designed characterization setup [11] that allows to execute
accelerated aging conditions. To this end, a versatile                  BTI/HCI aging tests over hundreds of CMOS transistors with a
transistor array chip and a flexible measurement setup have             stress parallelization technique that significantly reduces the
been used to reduce the required testing time to attainable             total aging test time.
values.
                                                                           II.     EXPERIMENTAL CHARACTERIZATION FRAMEWORK
 Keywords—CMOS; BTI; HCI; parameters; extraction; method;                   Transistor statistical characterization has been conducted
RTN; defects; aging;                                                    using our versatile ENDURANCE transistor array IC (Fig. 1a),
                                                                        fabricated in a commercial 1.2-V, 65-nm bulk CMOS
                         I. INTRODUCTION                                technology [5]. This IC allows individual access to thousands of
    With nowadays CMOS technology downscaling, Bias                     devices of various geometries for their individual
Temperature Instability (BTI) [1-2] and Hot Carrier Degradation         characterization. Full variability characterization can be
(HCI) [3-4] aging effects, as well as Random Telegraph Noise            accurately executed since each device under test (DUT) terminal
(RTN) [5] transient effects, have re-emerged as important time-         can be connected/disconnected in parallel to individual analog
dependent variability (TDV) phenomena that must be                      signal paths depending on the tests to be performed. In this
considered in order to achieve reliable designs of digital and          sense, DUT terminal connections are performed by means of
analog integrated circuits (ICs) [6-7]. During circuit operation,       appropriately sized full transmission gates (TG) designed using
the variability effects related to the trapping/detrapping of           thick IO transistors. Each DUT is accompanied by an individual
charge carriers in/from oxide defects could result in circuit           digital circuit that controls 8 TGs, i.e., 5 TGs for the drain and 3
malfunction due to the shift of key transistor parameters, such as      TGs for the gate, which connect the DUT drain and gate to the
the threshold voltage (Vth). Thus, it is critical for IC designers to   corresponding on-chip analog paths. In this scenario, Fig. 1(a)
consider TDV effects to implement reliability-aware circuits [6-        illustrates the distribution of the stress, measure and stand-by
8]. To this end, appropriate compact models, like the                   analog signal paths for drain and gate DUT off-chip biasing.
Probabilistic Defect Occupancy (PDO) model [8], are essential.
These models need to account for and clearly distinguish the                The IC design harbours 3,136 unit cells, each yielding access
‘slow’ defects, responsible for aging-induced degradation, from         to a single transistor with local force-&-sense connections to
the ‘fast’ defects causing the RTN transient variations [5]. As         mitigate on-chip voltage drops, as shown in Fig. 1(b). The unit
shown in this paper, isolating the impact of the different aging        cell circuit design, consists of two separate blocks: the digital
phenomena sources in the form of transistor degradation is not a        CONTROL core and the DUT block. The DUT block contains a
straightforward task.                                                   single nMOS or pMOS transistor with two analog connections:
                                                                        the drain connection and the gate connection. The CONTROL
    Another important aspect is that an accurate transistor             core block consists of 3-bit individual memories to store the
characterization requires a robust statistical characterization of      required operation mode of the unit cell, and a level shifter block
the transistor response to accelerated stress conditions due to the     that performs the necessary voltage level shift of all TG control
stochastic nature that TDV phenomena reveal in deeply-scaled            signals from 1.2V of the digital circuitry up to the 3.3V operation
technologies [9]. Conventional BTI/HCI aging characterization           voltage level of the I/O transistors.
Fig. 1. (a) High-level schematic illustration of the ENDURANCE chip design showing the array structure of unit cells and (b) the unit cell design
consisting of a single DUT with properly sized force-and-sense transmission gates and operation mode circuitry [5]
    Extensive and accurate statistical transistor characterization         time required for measurement of the remaining DUTs in cycle
has been conducted by means of our automated flexible                      C1 (time A). If the difference is negative (B<A), the algorithm
characterization setup that allows executing parallel TDV tests            inserts the necessary standby period (SB, in green in Fig. 2) to
over hundreds of devices simultaneously. To the best of the                avoid any measurement overlap.
authors’ knowledge, this is the first array IC chip that allows HCI
parallel testing. Our novel all-DUT-parallel-stress-pipeline                            III.   SAMPLES AND STATISTICAL TESTS
measurement (ADPSPM) measurement technique (Fig. 2),                           Prior to the realization of any TDV test, more than 40,000
designed to accommodate Measurement Stress Measurement                     transistors from 15 ENDURANCE chips have been evaluated at
(MSM) test sequences in a parallel-pipelined scheme, has been              their nominal operating conditions (|VGS|≤1.2V and |VDS|≤1.2V)
utilized to significantly reduce the required aging test time from         to assess the intra- and inter-die process variability (i.e., time-
several months or years to a few days [11]. Notice that the first          zero variability, TZV). In this regard, Fig. 3 shows the empirical
measurement cycle does not appear in Fig. 2, since the                     Cumulative Distribution Function (CDFs) of the initial device
measurement of the pristine characteristics of the devices can be          threshold voltage |Vth0|, which properly fits gaussian
performed at any point and does not need to be accommodated                distributions. Statistical die-to-die |Vth0| dispersion exhibits
within the ADPSPM timing scheme. In the first SM cycle (C1,                small variability as shown by the compactness of the CDFs
in orange in Fig. 2), the SM pattern of each DUT is delayed                measured on different chips (~16mV/~23mV for nMOS/pMOS
ensuring that all the measurement phases in all DUTs are                   for 50% of devices). However, considerable device-to-device
correctly pipelined. Once all the SM patterns of cycle C1 have             variability is observed (~350mV/~250mV for nMOS/pMOS).
been temporarily allocated, the algorithm starts the parallel
distribution of the next cycle (C2). Since the setup and the chip             After the TZV tests, extensive BTI and HCI accelerated tests
allow the parallelization of the stress, but not of the                    have been conducted on these devices at different test
measurement, the critical condition is that the last measurement
phase of cycle C1 (for DUT#5) cannot overlap with the first
measurement phase of cycle C2 (for DUT#1). To comply with
this critical condition, the algorithm computes the total SM time
needed for DUT#1 in cycle C2 (time B) and compares it to the




Fig. 2. Illustration of the ADPSPM test technique utilized in this study
to drastically reduce the aging testing time. 5 DUTs are shown during
a 4-cycle SM test. C1 illustrates the first SM pattern. Interval A
denotes the time reserved for other DUTs measurements after the end        Fig. 3. Empirical CDFs of the |Vth0| parameter for the 80nm/60nm
of the DUT#1 SM cycle and interval B is the required time for the SM       pristine nMOS (a) and pMOS (b) transistors of 15 different ICs. Die-
pattern execution of DUT#1 in the next cycle [6].                          to-die variation is much smaller than the intra-die variability.
                                                                             Fig. 6. HCI recovery traces of pMOS transistors after a stress time of
                                                                             10ks at |VDS| = |VGS| = 1.2V, T = 25ºC showing less discrete ∆|Vth|
                                                                             discharges than for NBTI (Fig. 5), while RTN is also present in almost
                                                                             all traces.
Fig. 4. Summary tables of the BTI (top) and HCI (bottom) conducted
aging tests in this study. Each table specifies the total number of tested   decreased. HCI-stressed devices (Fig. 6) can show larger Δ|Vth|
devices for each test, temperature and voltage stress conditions, the        and reveal less discrete defect discharges, resulting in a more
amount of devices for each |VGS|;|VDS| condition and the test time           ‘permanent’ damage that NBTI-stressed ones. Moreover, RTN
comparison in days (d) between serial and ADPSPM methods.                    is present in almost every trace.
conditions. Fig. 4 summarizes the aging tests, which consisted                   The statistical ∆|Vth| variability for the different stress
in 5-cycles MSM sequences, where stress times are increased                  voltage/temperature conditions has been evaluated, as a function
logarithmically, i.e., 1s, 10s 100s, 1ks and 10ks, while                     of the stress time. Two examples of CDFs are shown in Fig. 7
measurement times are fixed to 100s. In total, 6,418 transistors             for BTI and HCI tests on pMOS at nominal (1.2V) (Fig. 7a and
have been tested using the ADPSPM technique. The total test                  7b) and accelerated (2.5V) (Fig. 7c and 7d) conditions. Fig. 7a
time was 37 days, which is experimentally feasible, instead of               and Fig. 7b show that ∆|Vth| increases with time, being the shifts
the 2.36 years needed if serial tests had been performed. The
advantage of our approach becomes even more evident when an
additional sixth stress cycle of 100ks is added to this test: 45 days
versus 22 years with the standard serial approach.
    To evaluate device degradation after each stress phase,
device recovery current traces were measured at |VDS| = 0.1V
and VGS ≈ Vth0 for 100s. Some examples are shown in Figs. 5
and 6, which correspond to threshold voltage shift vs, time
(∆|Vth|-t) traces measured on pMOS after NBTI tests at |VDS| =
0V and |VGS| = 1.2V (Fig. 5), and HCI tests at |VDS| = |VGS| =
1.2V (Fig. 6). Note that the nominal operation voltage of the
technology was applied to ‘stress’ the devices. However, even in
this case with relatively short stress periods, the NBTI-biased
devices show changes in their threshold voltage during the
measurement phase, with multiple defect discharges that drive
Vth towards its pristine value once that the applied voltage is




                                                                             Fig.7: CDFs of the ∆|Vth| values measured on the pMOS after 100s
                                                                             of recovery for several stress times at T=25ªC. (a) NBTI and (b) HCI
Fig.5. NBTI recovery traces measured on pMOS after a stress time of          at 1.2V (nominal conditions). (c) NBTI and (d) HCI accelerated
10ks at |VDS| = 0V, |VGS| = 1.2V and T = 25ºC showing multiple               stresses at 2.5V. ∆|Vth| <0 is also present because of the significant
discrete defect discharges combined with RTN and background noise.           impact of RTN.
larger when |VDS|≠0. However, the observed shifts can be              [3] Duan M, Zhang JF, Ji Z, Zhang WD, Kaczer B, Asenov A.
comparable to those introduced by TZV. Moreover, the strong           Key Issues and Solutions for Characterizing Hot Carrier Aging
presence of RTN before and after device stress, results in ∆|Vth|     of Nanometer Scale nMOSFETs. IEEE Trans Electron Devices
< 0V for some devices, as observed in Fig. 7a, b and c. As            2017;64:2478–84. doi:10.1109/TED.2017.2691008.
expected, the most severe accelerated stress conditions (HCI at
2.5V, Fig. 7d) clearly show larger ∆|Vth| shifts. These results       [4] Martín-Martínez J, Gerardin S, Amat E, Rodríguez R,
suggest that the voltage dependence of TDV threshold voltage          Nafría M, Aymerich X, et al. Channel-hot-carrier degradation
shifts can be accurately studied incorporating data obtained at       and bias temperature instabilities in CMOS inverters. IEEE
nominal operation conditions.                                         Trans        Electron        Devices       2009;56:2155–9.
                                                                      doi:10.1109/TED.2009.2026206.
                           CONCLUSION
                                                                      [5] Diaz-Fortuny J, Martin-Martinez J, Rodriguez R, Nafria M,
    This work presents statistical MOSFET TDV data obtained
                                                                      Castro-Lopez R, Roca E, Fernandez FV. A noise and RTN-
by means of a versatile array-IC chip together with the ADPSPM
test parallelization technique. This parallelization allows a large   removal smart method for parameters extraction of CMOS aging
reduction in the necessary test times (i.e., from years to a few      compact models. In 2018 Joint International EUROSOI
days). This enables the statistical characterization of thousands     Workshop and International Conference on Ultimate Integration
of devices under a large range of stress conditions, such as          on Silicon (EUROSOI-ULIS) 2018 Mar 19 (pp. 1-4). IEEE.
nominal and overvoltage operation conditions. Such tests have         [6] Toro-Frias A, Martin-Lloret P, Martín-Martínez J, Castro-
been performed both for BTI and HCI phenomena at different            López R, Roca E, Rodríguez R, Nafria M, Fernández FV.
temperatures, and the obtained statistical results have been          Reliability simulation for analog ICs: Goals, solutions, and
discussed. BTI and HCI experiments performed at nominal
                                                                      challenges. Integration. 2016 Sep 1;55:341-8.
voltages also revealed Vth shifts in the devices, showing
recovery when the applied voltages were decreased. However,           [7] Rzepa G, et al. "Comphy—A compact-physics framework
at these conditions, the TDV related shifts are comparable to         for unified modeling of BTI." Microelectronics Reliability 85
those introduced by TZV. . Moreover, RTN was observed                 (2018): 49-65.
simultaneously to the Vth shifts..These results suggest that,
because the strong reduction of the testing time allowed by the       [8] Martin-Martinez J, Kaczer B, Toledano-Luque M, Rodriguez
set-up, data obtained at nominal operation conditions can be          R, Nafria M, Aymerich X, Groeseneken G. Probabilistic defect
incorporated into the aging modelling.                                occupancy model for NBTI. In2011 International Reliability
                                                                      Physics Symposium 2011 Apr 10 (pp. XT-4), IEEE.
                      ACKNOWLEDGEMENTS
                                                                      [9] Kaczer B, Grasser T, Roussel J, Martin-Martinez J,
    This work has been supported in part by the Spanish               O’Connor R, O’Sullivan BJ, et al. Ubiquitous relaxation in BTI
TOGETHER Project TEC2016-75151-C3-R (AEI/FEDER, UE)
                                                                      stressing-new evaluation and insights. Proc. Int. Reliab. Phys.
and by the VIGILANT Project (PID2019-103869RB / AEI /
10.13039/501100011033).        Pablo    Sarazá  Canflanca             Symp.,          IEEE;          2008,          p.          20–7.
acknowledges MICINN for supporting his research activity              doi:10.1109/RELPHY.2008.4558858.
through the predoctoral grant BES- 2017-080160.                       [10] Diaz-Fortuny J, Martin-Martinez J, Rodriguez R, Nafria M,
                                                                      Castro-Lopez R, Roca E, et al. A transistor array chip for the
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