This is the accepted version of the article: Pedreira Rincon, Gerard; Martin Martinez, Javier; Saraza-Canflanca, Pablo; [et al.]. «Unified RTN and BTI statistical compact modeling from a defect-centric perspective». Solid-State Electronics, Vol. 185 (November 2021), p. 108112. DOI 10.1016/j.sse.2021.108112 This version is available at https://ddd.uab.cat/record/249450 under the terms of the license Unified RTN and BTI statistical compact modeling from a defect-centric perspective G. Pedreira1, J. Martin-Martinez*1, P. Saraza-Canflanca2, R. Castro-Lopez2, R. Rodriguez1, E. Roca2, F. V. Fernandez2, M. Nafria1 1Universitat Autònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain 2Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain E-mail address of corresponding author: javier.martin.martinez@uab.es Abstract— In nowadays deeply scaled CMOS technologies, characterization setup [11] to measure RTN and BTI from the time-dependent variability effects have become important near threshold until elevated stress voltages. Also, the nominal concerns for analog and digital circuit design. Transistor operating conditions of the devices are included in the study. parameter shifts caused by Bias Temperature Instability From the experimental results the interplaying role of RTN and and Random Telegraph Noise phenomena can lead to BTI is discussed. Moreover, both phenomena are statistically deviations of the circuit performance or even to its fatal modeled using a common framework that fully describes the failure. In this scenario extensive and accurate device simultaneous impact of both phenomena in a wide voltage characterization under several test conditions has become range. The physical interpretation of the model parameters and an unavoidable step towards trustworthy implementing the their dependences with the measurement conditions are stochastic reliability models. In this paper, the statistical provided. distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, II. EXPERIMENTAL CHARACTERIZATION nominal and accelerated aging conditions. Statistical Devices used for this work were pMOS transistors with modelling of RTN and BTI combined effects covering the W/L=80nm/60nm. First, the ID-VG characteristic was measured full voltage range is presented. The results of this work to obtain the initial threshold voltage of each device Vth0. After suppose a complete modelling approach of BTI and RTN that, devices were subjected to a Measurement-Stress- that can be applied in a wide range of voltages for reliability Measurement (MSM) scheme [12] (Fig. 1a). The stress phases predictions. were applied with duration of tS=1s, 10s, 100s and 1000s and a gate voltage Vs=-1.2V, -1.5V, -2V and -2.5V while the other Keywords—CMOS; BTI; RTN; defects; modelling; terminals were grounded. Although we will refer to the stress characterization; Reliability phase when we apply the voltage VS to the device at the gate, I. INTRODUCTION because this is the usual nomenclature, however, in the case of Vs = -1.2V we cannot consider that the devices are actually Time-Dependent Variability (TDV) in deeply scaled CMOS subjected to accelerated electrical stress, since they are technologies has become a serious concern that negatively polarized under nominal operating conditions. During the impact device and circuit performances [1]. TDV includes, measurement phases that follow the stress phases, with a among others, transient effects such as Random Telegraph duration of tm=100s, the drain current was continuously Noise (RTN) [2,3] and Bias Temperature Instability (BTI) measured applying Vm=-0.6V to the gate and VD=-100mV to [4,5]. Because of the common origin of both phenomena [5], the drain. From this current, the threshold voltage after the i.e., charge trapping/detrapping in/from defects in MOSFETs, stress, Vthf, was calculated with the method presented in [11]. they should be modeled together to improve the accuracy in To extend the studied range of voltages, the data presented in evaluating circuit reliability [6]. However, the stochastic nature [10] at VS=-0.6V is also included in our analysis. One of the of defects requires that many devices at the same conditions advantages of our test scheme (i.e. ENDURANCE chip + have to be measured to perform complete statistical studies. flexible characterization set-up), whose details are explained in Moreover, RTN and BTI are strongly dependent of the biasing [9], is that the stress phase of many devices can be parallelized, conditions of the devices, then, a complete characterization of so that the required testing time is drastically reduced. In this both phenomena requires the measurement of many devices at work, 200 devices were tested for each VS condition, which several biasing conditions. From the above it is concluded that means that more than 100 days would have been required statistical studies of RTN and BTI requires advanced without parallelization. However, using our approach, all the characterization strategies for massive device characterization measurements were performed in less than one week. For each in reasonable measurement times. The most extended solution device, the threshold voltage shift ΔVth=|Vthf|-|Vth0| was for this problem is the use of designed array-based Integrated calculated to evaluate the effect of the stress in the device. Fig. Circuits (ICs) to parallelize the measurements and drastically 1b and Fig. 1c show examples of ΔVth as a function of the reducing the effective time required for the statistical measurement time, tm, for the cases of VS=-1.2V (the nominal characterization in many devices [7-9]. In this work, we take operation voltage of the considered technology) and VS=-2.5V. advantage of the ENDURANCE chip [10] and a flexible It can be observed that, at VS=-1.2V, ΔVth alternates between two different levels, which indicates that RTN is below, extending the applicability of our previous approach. dominating the Vth fluctuations (Fig. 1b); however, for VS=- The starting point is our previous work [13], where we 2.5V several Vth drops can be observed, which correspond to demonstrated that in near-threshold biasing conditions, ΔVth the emission of charges that have been trapped during the distributions can be modeled considering eq.1 previous stress phases, (Fig. 1c), which is typical of BTI. ∆𝑉 η , 𝑜𝑐 𝑡 𝑜𝑐 t 0 𝑟𝑎𝑛𝑑𝑛 𝜎 𝑒𝑞. 1 where N0 is the number of active defects in the device before biasing and ɳ0,i is the Vth shift caused by the trapping/detrapping in the i-th defect. oci is the defect occupancy state, which is 1, if occupied, or 0, if empty. The term randn(σ) represents a random number (from a Gaussian distribution with mean value 0 and standard deviation σ), which is included to account for the background noise in the experimental setup. We consider that N0 and ɳ0, follow Poisson and exponential distributions respectively [14]. In [13] was demonstrated that Vth shift distributions related to RTN can be modeled using eq. 1 considering that the mean values of the N0 and ɳ0 distributions are =1.37 and <ɳ0>=3.2mV, Fig. 1. (a) MSM scheme used to investigate RTN and BTI in pMOS respectively. Note that, in that case, low voltages were applied, devices. b and c) ΔVth evolution in 2 pMOS devices so that BTI-related trapping was expected to be negligible. (W/L=80nm/60nm) measured at Vm = 0.6V, for the cases of (b) However, in the case of the voltage range in this work (that VS = 1.2V and (c) VS= 2.5V. ΔVth is defined as the difference covers from nominal to high stress voltages), eq.1 is not enough between Vth(tm) and Vth measured on the pristine device. to describe the ΔVth distributions, because the trapping probability increases with the applied voltage. Consequently, Results of Fig. 1b and c are illustrative examples of our eq.1 has been modified, adding an additional summation term, measurements, however due to the stochastic behavior of to consider this trapping probability increase at larger voltages, defects large spread is expected in measurements performed leading to eq.2 under nominally identical conditions. Therefore, for a useful modeling of the phenomenology it is convenient to statistically analyze the results. Is for that reason than Fig. 2 shows the ΔVth ∆𝑉 η , 𝑜𝑐 𝑡 𝑜𝑐 t 0 η , 𝑟𝑎𝑛𝑑𝑛 𝜎 𝑒𝑞. 2 cumulative distribution functions after tests at VS= 1.2V and VS= 2.5V of different duration, tS. Positive/negative values of The first and third terms are those already included in eq. 1 (low ΔVth can be attributed to a net trapping/detrapping process voltage range), whereas the increase of the trapping probability during the test. The symmetry of the distributions at VS=1.2V is accounted for in the second summation term. There, NS is the hints at a similar number of trapping and detrapping events, number of defects that have been occupied in the device at which is consistent with the dominant presence of RTN, as larger voltages and ɳs,i is the Vth shift linked to these defects. shown in Fig. 1b. Many devices show ΔVth=0, which indicates As for N0 and ɳ0, Poisson and exponential distributions are also that either there are no defects in the device or, if there are, they assumed for NS and ɳS, with mean values and <ɳS>, do not effectively change their occupancy state during the respectively. With these assumptions, eq. 2 is able to reproduce measurement. For VS=2.5V, ΔVth rapidly increases with tS the experimental ΔVth distributions in Fig. 3. because of the larger trapping probability for larger stress times. Trapping also increases (and, thus, ΔVth) with VS (Fig. 3a). In Fig. 3b, the shift of the distributions to lower values as tm increases indicates the progressive detrapping of charges that were trapped during the stress. As in Fig. 2, the distributions in Note that for all the ΔVth distributions of Fig. 2 and Fig. 3 ΔVth is negative in the low percentile tails, which implies that a net detrapping is not negligible. Therefore, even for the most aggressive stress conditions applied (VS=-2.5V) detrapping can be relevant and consequently should be considered for modeling purposes. III. MODELLING THE VTH DISTRIBUTIONS Fig. 2. Examples of ΔVth distributions measured at tm=100s for To describe all these observations, a simple model, based on different values of VS and ts. 200 devices are considered in each the trapping/detrapping of charges in/from defects, is presented distribution. Fig. 3 ΔVth distributions obtained for (a) different VS and (b) different Fig. 4. as a function of the stress and measurement conditions measurement times, tm. Lines show the fittings obtained with eq. 2. VS, ts and tm. The only fitting parameters here are and <ɳS>, because In order to provide a simple kinetics model valid for the the values of =1.37 and <ɳ0>=3.2mV have been fixed to considered technology, has been described using the the values determined from the measurements at low voltages following semiempirical expression based in the Universal [13], since they must be kept unchanged to ensure that eq. 2 is Relaxation Function for BTI [13] consistent in all the voltage range (high and low voltages). The 𝑁 𝑒𝑞. 3 good fitting of the experimental data demonstrates that the / inclusion of the second summation, despite its simplicity, is Fig. 5a shows the fittings of to eq. 3 for ts=1,000s, sufficient to describe the ΔVth distributions measured when while the extracted values of the parameters α, β and B are RTN and BTI aging are simultaneously active. Then, clearly the given in Table 1. Fig. 5b shows that the K parameter fits to a effects of stress must be reflected in the NS and ɳS distributions, power law with VS. that is, in the and <ɳS> parameters. |VS| (V) α B β The full modelling of the ΔVth distributions requires the 1.2 0.22 11.49 0.68 evaluation of their dependencies on the biasing conditions, so 1.5 0.26 2.67 0.34 that the voltage dependencies of and <ɳS>have been 2.0 0.098 2.88 0.32 analysed. Fig. 4 shows as a function of the stress tS, and 2.5 0.066 2.01 0.15 measurement, tm, times for different values of VS. Note that Table 1 : α, β and B values of eq. 3 obtained at the different is the only parameter required to describe the statistical voltage conditions tested. distribution of NS, therefore, the results in Fig 4 are enough to estimate the number of defects that in a device will be charged as a consequence of the stress. In the time range investigated, logarithmically increases with tS, due to charge trapping during the stress, and logarithmically decreases with tm , due to detrapping of previously trapped charges during measurement at lower voltages. As expected, the number of defects that trap charges increases with VS. If we compare the results of Fig. 4 with those at lower voltages (i.e. =1.37), it is clear that for |VS|≤1.5V the number of defects , , is smaller than , though the contribution of should not be considered negligible. If |VS|≥2V, is clearly larger than , but even in the most aggressive biasing tested condition (VS=- Fig. 5.(a) fitting to eq. 3 for ts=1,000s. (b) The K parameter of 2.5V, ts=1000s and tm=10ms), its value (=6.7) is not large eq. 3 follows a power law dependence with VS. enough to consider that the contribution of is negligible. Then, from this discussion, we can conclude that for the Finally, we have investigated the dependence of <ɳS> with description of the ΔVth in a large voltage range (from near- the voltage conditions. It should be remarked that <ɳS> is the threshold up to voltages much larger than the nominal), the only parameter needed to evaluate the ɳS distribution, therefore whole set of active defects should be considered. That is, those it is enough to describe the magnitude of the Vth shift at the defects that would be only observed at low voltages (leading to larger voltages. The symbols in Fig. 6 shows the estimated <ɳS> RTN) and those that will be only activated at the larger voltages at tm=2ms and ts=100s for the investigated VS from the fitting (observed as BTI). of the Vth shift distributions. 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