This is the accepted version of the article: Ntinas, Vasileios; Rubio, Antonio; Sirakoulis, Georgios Ch; [et al.]. «Power- efficient noise-induced reduction of reram cell’s temporal variability effects». IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, issue 4 (April 2021), p. 1378-1382. DOI 10.1109/TCSII.2020.3026950 This version is available at https://ddd.uab.cat/record/248834 under the terms of the license 1 Power-efficient Noise-Induced Reduction of ReRAM Cell’s Temporal Variability Effects Vasileios Ntinas, Student Member, IEEE, Antonio Rubio, Senior Member, IEEE, Georgios Ch. Sirakoulis, Member, IEEE, Emili Salvador Aguilera, Marta Pedro, Albert Crespo-Yepes, Javier Martin-Martinez, Rosana Rodriguez, Senior Member, IEEE, and Montserrat Nafria, Senior Member, IEEE Abstract—Resistive Random Access Memory (ReRAM) is a (ReRAM) stands out, since it presents high scalability and promising novel memory technology for non-volatile storing, low fabrication cost, long retention and compatibility with 3D- with low-power operation and ultra-high area density. However, integration, while it performs adequately in terms of latency, ReRAM memories still face issues through commercialization, mainly owing to the fact that the high fabrication variations and energy consumption, endurance, and multi-level computing the stochastic switching of the manufactured ReRAM devices [3]. However, as indicated in [3], the unique problematic cause high Bit Error Rate (BER). Given that ReRAM devices aspect for this category of emerging devices is their variability are nonlinear elements, the nonlinear phenomenon of Stochastic [4]–[6]. As a result, this major issue of the ReRAM devices Resonance (SR), which defines that an input disturbance with affects heavily the commercialization of ReRAM-based prod- specific characteristics can improve the total performance of the nonlinear system, is used to reduce the ReRAM cell’s ucts, due to the reduced robustness of such systems. BER. Thus, in this work, the BER of a single ReRAM cell In this letter, the nonlinear phenomenon that is known as is explored, using the Stanford PKU model, and is improved Stochastic Resonance (SR) [7] is utilized against the negative after the application of specific additive input noise. The power effects of the device’s stochasticity on memory applications. dissipation of the proposed approach is also evaluated and In particular, a single ReRAM cell’s temporal (cycle-to-cycle) compared with the consideration of higher amplitude writing pulses in the lack of noise, showing that the proposed noise- variability, which strongly affects the Bit Error Rate (BER) of induced technique can decrease the BER without the excessive ReRAM memories, is exposed to a noise-induced SR-based increase of the power dissipation. As a first step, towards the writing method, showing rather interesting reduction of BER experimental verification of the proposed method, noise-induced and resulting to an increased system’s performance. More measurements on a single fabricated ReRAM device are also specifically, SR describes how a noisy input excitation can performed. Overall, the presented results of the BER reduction with low power dissipation, reaching up to 3.26× less power achieve better output performance compared to the original consumption considering 100 ns writing pulses, are encouraging non-noisy input. The concept of exploiting SR on memristor’s for ReRAM designers, delivering a circuit-level solution against switching enhancement was, firstly, explored in [8] by intro- the device-level problem. ducing internal stochasticity to the memristor model, as well Index Terms—ReRAM devices, Memristor, Variability, as in [9], where the external application of additive noise was Stochastic Resonance, Emerging Memories investigated, showing that memristor’s maximum to minimum resistance ratio can be enhanced. Given that the aforemen- tioned ratio affects the read margins of a ReRAM-based I. I NTRODUCTION memory and that the ReRAM-device switching is attributed to I nternet-of-Things, Big Data, and Artificial Intelligence constitute a great share of the demanding applications that are pushing today’s computing systems to their limits highly nonlinear physical mechanisms, this work focuses on the Bit Error Rate (BER) of single variability-aware ReRAM cell and utilizes SR on the BER’s reduction with additive [1]. Today’s computer capabilities need further scaling up to noise along with the writing pulses, reaching up to 3.26× less cover the rapidly increasing demand for information storing power consumption. Likewise, for the first time, the power and processing. Aiming to continue the scaling up of com- consumption of the noise-induced approach is investigated puters’ performance, novel memory technologies are under as a practical advantage of the method and is bench-marked development to extend the memory capabilities nearby or against the sweep of the writing pulses’ amplitude without within the processing units by their ultra-dense packing, re- the presence of input noise. As a proof of concept, the noise- programmability, and by bringing non-volatile storage inside induced approach is tested on a standalone fabricated Hafnium the chip [2]. In particular, among the emerging memory can- Oxide device, illustrating the beneficial effect of the additive didates, the Metal-Oxide Bipolar Filamentary Resistive RAM input noise on actual Metal-Oxide ReRAM devices. V. N. and A. R. are with the Department of Electronics Engineering, Universitat Politécnica de Catalunya, Barcelona, Spain. G. Ch. S. and V. II. R E RAM C ELL AND B IT E RROR R ATE N., also, are with Department of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece. E. S. A., M. P., A. C.- The modeling of two-terminal thin-film devices like Y., J. M.-M., R. R. and M. N. are with Department d’Enginyeria Electrónica, Universitat Autónoma de Barcelona, Spain. ReRAMs, is yet a non-trivial procedure; thus, currently, there Manuscript received April XX, 2020; revised XXXXXX XX, XXXX. This is a vast amount of various models in the literature [10], [11]. work was supported in part by Spanish MICIU under Project PID2019- In this work, the Stanford-PKU ReRAM device model [12] 103869RB-C33 and in part by FPI-UPC and partially supported by Greece- Russia bilateral joint research project MEM-Q (proj.no./MIS T4∆PΩ- has been utilized because it is a physics-based model, which 00030/5021467) supported by GSRT, funded by National and European funds. can accurately describe the behavior of actual oxide-based 2 (a) 10-3 (a) (b) |IReRAM| (A) 10-4 Fig. 2. Distribution of read values for a benchmark scheme using the Stanfond-PKU ReRAM model without (a) and with (b) temporal variability. The symbols correspond to R0 (stars) and R1 (circles) readings, while the 10-5 bars to the R0 (blue) and R1 (orange) distributions (right axis). 10-6 0 100 125 225 250 writing pulse [12]. Figs. 1(b)-(c) illustrate a cycle of ReRAM time (ns) cell programming, consisting of a W0 and a W1 pulse and a (b) (c) corresponding R pulse, with VR = 1 V and shorter duration Fig. 1. (a) ReRAM cell circuit. (b) VW L , VBL , and (c) |IReRAM | during tread = 25 ns, after each writing pulse, defined as a W0 −R0 − a W0 − R0 − W1 − R1 cycle. W1 −R1 cycle. Fig. 1(b) shows the applied Word-Line voltage ReRAM devices by modeling the conductive filament’s (CF) VW L (blue) and Bit-Line voltage VBL (orange), while Fig. 1(c) growth within the insulating layer of the device. Furthermore, illustrates the modulus of current through the ReRAM device the Stanford-PKU ReRAM device model has been developed in log-scale. All the simulations have been performed with the on Hafnium Oxide Metal-Insulator-Metal devices [13] exactly SPECTRE simulator in the Cadence Virtuoso platform. like the experimental device employed in Section V, enabling For memory devices, the BER is an essential metric to a good estimation of the behavior of the fabricated devices. evaluate the robustness of the system. The BER is calculated In addition, one of the most significant features of this model as the percentage of wrongly written bits out of the total is its ability to incorporate the device’s current fluctuations amount of writing processes. To further investigate the effect by employing stochastic processes in the growth of the CF, of the ReRAM device’s temporal variability to the BER, the causing the temporal variation of the device that results in the Stanford-PKU model’s feature for stochastic fluctuations of the increased BER of the ReRAM-based memory cells. CF’s growth is utilized. In particular, by adjusting the values Using this ReRAM device model, the functionality and for the intensity of CF’s gap and width fluctuations ({δg , δr }) the circuitry of a ReRAM memory cell is now explored. of the model [14], the ReRAM cell’s BER is modified. More specifically, logical ‘0’ (logical ‘1’) is mapped to the To measure the ReRAM cell’s BER, a benchmark scheme device’s high (low) resistive state, which can be written to has been set up. In detail, this benchmark scheme is a set of the cell by the application of a strong negative (positive) 100 W0 − R0 − W1 − R1 cycles applied to the ReRAM cell voltage. Since the resistance value cannot be read directly, and the voltage across the reading transistor TR in the middle the reading process comprises a short-amplitude positive pulse of the reading pulses is used to evaluate the correctness of the that maps the resistive state to voltage with the assistance of previously applied writing process. By measuring the voltage a properly-gated reference read transistor TR , based on the across the reading transistor, the current resistance value of voltage divider between the ReRAM device and the resistance the ReRAM device can be extracted using the formula of the of TR (Fig. 1(a)). The circuit configuration of such a cell is voltage divider. Practically, this benchmark scheme succeeds rather simple due to the memory capabilities of the ReRAM to measure the BER of each of W0 and W1 processes with device which can maintain its resistive state without the need 1% accuracy, while the alternation between them stresses the for any refresh voltage. So, the cell’s circuit (Fig. 1(a)) is device’s switching dynamics and amplifies the effect of vari- composed of the ReRAM device in series with a transistor- ability. Figs. 2(a) and (b) present the distribution of the read selector TSEL that also performs a protective current-limiter, voltages during R0 and R1 of one paradigmatic benchmark while the write and read signals are applied through the Bitline simulation without and with CF fluctuations, accordingly. (VBL ) and the Wordline (VW L ), respectively. For performing In the lack of fluctuations, it is clear that there is no temporal the reading process, TR is mainly used like here, i.e. inside variability, so the read voltage after every writing process is the cell, to implement the necessary voltage divider able to fixed. On the contrary, the results in the case with fluctuations distinguish the two states. However, in a large array, TR will are scattered. Firstly, the read voltage after W0 is distributed be modified according to the corresponding reading scheme. throughout almost all the range of possible values, with higher The stored cell bit is read at the intermediate node, during the number of occurrences on the lower part of this range. On reading process when TSEL is open and TR is closed. the other hand, after W1 the read voltage is mostly at the In Stanford-PKU model, the RESET (W0 ) and SET (W1 ) same value as in the no-fluctuations case. However, there is processes can be performed by applying negative and positive a considerable number of cases that the writing pulse was pulses, accordingly, with amplitude VW = |2| V and pulse not able to SET the ReRAM device due to its previously width τ = 80 ns. Also, the rising and falling edge duration of achieved very high resistance state. To calculate the BER of each pulse is τr/f = 10 ns, resulting in a total of 100 ns per the performed simulations, the erroneous bits of W0 (W1 ) 3 1 W0 W1 Total (V) (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.1 3e-12 1e-16 BER Energy (J) 0.01 5e-17 W0 W1 R0 R1 0.001 1e-13 0.0001 0 0.3 0.6 0.9 1.2 1.5 5e-15 1e-17 (V) 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 VPULSE (V) VPULSE (V) Fig. 3. BER scaling for W0 , W1 and Total BER of the ReRAM cell with additive noise for 300 benchmark schemes per σ value. The purple dashed Fig. 5. Total energy consumption for each pulse of the W0 − R0 − W1 − R1 line depicts the average BER without external noise source. cycle for varying VP U LSE and σ. Full (dashed) line corresponds to the amplitude (noise intensity) sweep and is mapped to the bottom (top) x-axis. 25 10 -4 20 2V + Noise standard deviation σ is varying. Fig. 3 presents the evaluated 2V Power ( W) Power (W) 15 2.7V 10 -6 BER of W0 , W1 and the Total BER in regards to the value of σ in each simulation, in the range σ = [0.05, 0.1, ..., 1.5] V. 10 10 -8 For each value of σ, 300 benchmark simulations are performed 5 and the average is illustrated in Fig. 3, whilst the average BER 0 W0 R0 W1 R1 10 -10 W0 R0 W1 R1 without additive noise is indicated by the purple dashed line. (a) (b) The acquired results indicate a positive impact of the additive noise against the BER. In details, the BER of W1 Fig. 4. Power dissipation during a benchmark cycle W0 − R0 − W1 − R1 with (σ = 0.35V) and without noise in (a) linear and (b) logarithmic scale. processes was reduced to zero, using σ > 0.2 V, which indicates that the noise assisted to the activation of the SET processes are identified when the reading value belongs either process of the ReRAM device and the “stuck-at-zero” cases of to the Logic1 (Logic0 ) area or the Grey zone area, i.e. for Fig. 2(b) (orange circles at Logic0 regime) were diminished. a read voltage higher than 0.4 V (lower than 0.6 V). These On the other hand, the BER’s improvement for the W0 limits are depicted in Fig. 2(b) by the vertical black and red processes is lower but stronger noise signals are required to dashed lines that were selected appropriately to define a Grey achieve zero BER values. In total, as it is anticipated by the SR zone where the cell’s logic state is unidentifiable. theory, the noise-induced performance improvement follows a The presented simulation results for the fluctuations case curve that exhibits a peak value for a specific noise’s intensity, were acquired with {δg , δr } = {1, 5}, which are much higher corresponding to the value of σ, and beyond that peak the than the values originally proposed in the Stanford-PKU model improvement is reduced, leading to a detrimental effect of [14]. However, the selected values enable the successful study noise on the performance, as illustrated in Fig. 3. of the temporal variability without the need for long and time- consuming simulations with thousands of pulses. IV. P OWER D ISSIPATION While the use of additive noise to reduce the ReRAM cell’s III. S TOCHASTIC R ESONANCE A PPROACH BER presents positive results against temporal variability, it is To study the potential improvement of the ReRAM cell’s not the only method to tackle with it. A more common way to BER, the writing pulses, both W0 and W1 , have been enriched counterbalance the negative effect of temporal variability and with additive white Gaussian noise to assist on the activation of decrease the BER of memory is to increase the amplitude of RESET and SET processes. White noise signals, theoretically, the writing pulses [16]. As long as the ReRAM device is a cover all the frequency spectrum, so they contain a small resistive element, the amplitude increase of the applied voltage portion of every frequency; however, during the simulations, V results to the ReRAM cell’s power dissipation increase in a the maximum achievable frequency is constrained by the nonlinear way, following the formula P = V 2 /R, where P is simulation step. Nevertheless, the ReRAM devices are less the dissipated power and R the resistance of resistive element. affected by signals with higher frequency than their operational Thus, in this Section, the power dissipation of the proposed frequency because their switching capabilities are diminishing approach is under study. In particular, the proposed approach is with the increase of frequency and they act as a regular fixed- compared with the increase of writing pulse amplitude without value resistor. Albeit, in this study, the white noise signal noise, taking into account both the power consumption and functions in an auxiliary way to the writing signal by assisting the BER of each case. First of all, the power dissipation of to the activation of the device switching; while, the additive a sole W0 − R0 − W1 − R1 cycle without device variability noise signals are generated by a zero-mean Gaussian Process is studied, in order to evaluate the power dissipation of each (<ξ>= 0) with covariance function <ξ(t)ξ(t0 )>= σ 2 δ(t−t0 ). pulse of the cycle, individually. In Fig. 4, the power dissipation Preliminary results on a small crossbar array [15] revealed that for the original writing pulse amplitude VP U LSE = |2| V this kind of noise can be beneficial. is illustrated in comparison with the power dissipation of a Using the benchmark scheme to evaluate the BER, a set no-noise pulse with VP U LSE = |2.7| V and a noisy one of simulations with the same parameters of the temporal with VP U LSE = |2| V and σ = 0.35 V, as an example. It variability example of Fig. 2(b) has been executed, with the is clear that the most power-hungry processes are the W1 integration of additive noise in the VW L . In specific, the and R1 , because the ReRAM device is driven towards the additive Gaussian noise has a mean value of µ = 0 V, while the low resistance state and the current through the device is 4 3.0V 15 3.0V Normalised (BER Power) 100 3.0V 15 10 Power (uW) 2.5V 2.5V 10 2.5V BER (%) 10 1 0.1 2.0V 5 2.0V 5 2.0V 0.02 0 1.5V 0 1.5V 0 1.5V 0 0.5 1 1.5 0 0.5 1 1.5 0 0.5 1 1.5 (V) (V) (V) (a) (b) (c) Fig. 6. (a) BER, (b) Power dissipation and (c) normalized BER×Power product for all the VP U LSE and σ combinations. The red line in (b) depicts the minimum power dissipation case per VP U LSE with minimum BER. higher. Between the different applied signals, during the W0 is required (for σ < 0.5 V) or the noise signal is strong enough and R0 , the original signal is not able to drive the ReRAM to corrupt the writing process (for σ > 0.9 V). Although device to very high resistance value and, as a result, the power the BER’s reduction can be achieved by both approaches, the consumption is higher than the other two signals. During the additive noise one is lower on power dissipation, as shown in W1 , all the signals can achieve the lower resistance state, so Fig. 6(b). In particular, even for high σ values, the power the more voltage is applied, the more power is dissipated. dissipation of the noisy signals with low VP U LSE is half Moreover, the noisy signal has a mean value of µ = 0V , compared to the no-noisy cases with high VP U LSE . However, and, as a result, the applied voltage is fluctuating around low power dissipation is also shown in the case with increased the VP U LSE , maintaining the power dissipation close to the BER because the ReRAM devices stuck at the high resistance original case. Finally, during the R0 , the current through the state. The red line in Fig. 6(b), which illustrates the minimum device is limited by TR , and, consequently, all the signals BER cases with the lowest dissipated power per VP U LSE , exhibit the same amount of dissipated power. clarifies the power-efficiency of the proposed method as the In a more detailed illustration of the power dissipation, ratio between the optimum no-noise ({2.6V, 0V}) and noise- Fig. 5 shows how the amount of dissipated power is scaling induced ({1.5V, 0.55V}) case for 100 ns writing pulses is with the increase of the VP U LSE and compares it with k = P{2.6V,0V} /P{1.5V,0.55V} = 5.68µW/1.74µW = 3.26. the increase of σ with fixed VP U LSE = 2 V (dashed Additionally, the combination of the BER and the power lines corresponding to the top x-axis) for each pulse of the dissipation is illustrated in Fig. 6(c) through the product W0 − R0 − W1 − R1 cycle. The power dissipation in Fig. 5 BER×Power. As long as the increase in either of those two is presented in the logarithmic scale and the superiority of the metrics is affecting negatively the quality of the system, their additive noise approach is clear in the W1 process, the most product can depict the aggregate improvement in regards to power-hungry case. For the W0 process, the additive noise {VP U LSE , σ}. The values in Fig. 6(c) are normalized by the approach can achieve the maximum resistance state before value of the nominal case {2V, 0V} and the value of BER is the other case, as it can be deducted from the corresponding used as “1+BER” for the better comparison of the zero-BER R0 line; however, for higher σ it consumes more power. cases. The points with low power dissipation but higher BER Overall, the additive noise approach can achieve lower power than the nominal, are discarded (i.e. dots in Fig. 6(c)) because dissipation than the case with increasing VP U LSE . their low power is attributed to the insufficient W1 process, so In the following, further exploration of power dissipation is the ReRAM device is stuck at low current state. performed for different values of VP U LSE within all the range of σ. For reasons of comparison, the benchmark scheme is V. SR ON E XPERIMENTAL DEVICES utilized and the BER for every simulation is evaluated along In order to show a proof-of-concept of the noise-induced with the total power dissipation during the scheme. As long as SR benefits on the advantageous Filamentary ReRAM devices, both the intrinsic current fluctuations of the ReRAM devices a set of experiments on a Hf-based ReRAM device is held. and the external additive noise are generated through stochastic Moreover, the pulse programming scheme of the previous processes, a single simulation cannot illustrate sufficiently the sections is adopted, targeting an actual application of SR in performance of the system for a specific set of VP U LSE and ReRAM-based memories. To do so, the SPA Agilent 4156C σ. Thus, 20 simulations per {VP U LSE , σ} pair are performed is utilized to both apply voltage on and measure the current to evaluate the average BER and average power dissipation through a tested ReRAM device, which consists of a 5×5 of each pair, which are presented in Figs. 6(a) and (b), µm2 TiN/Ti/10nm HfO2 /W structure. The applied voltage and respectively. More particularly, the value of σ is shown in the measured current for a W1 − R1 − W0 − R0 programming the x-axis, while the various VP U LSE values are mapped to cycle are illustrated in Fig. 7(a) for both cases, namely without the line color, corresponding to the right-side colorbars. and with noise. In the experimental setup, the tested ReRAM Focusing on the Fig. 6(a), one can observe the significant sample is forward polarized, thus a positive (negative) voltage reduction of BER for a specific range of σ, in full agreement results to the SET (RESET) of the device. with the results of the previous section, for every VP U LSE Investigating the presence of SR in such devices, the same value. Nevertheless, out of this range, either a higher VP U LSE ReRAM sample is exposed to a set of 400 consecutive 5 VApplied (V) 1.2 w/o Noise reduction. However, the efficiency of the proposed method w/ Noise becomes prominent when the effect on the combination of 0 -0.5 BER and Power dissipation is considered, showing that it is -1.2 able to reduce the BER with low power dissipation, reaching 10 up to 3.26× less power consumption at minimum BER for a |IMeasured| (mA) 100 ns pulse width consideration. Moreover, an early proof of 1 concept of the proposed technique is provided through fabri- W1 R1 W0 R0 0.1 cated experimental devices. Thus, throughout this manuscript, 0 0.5 1 1.5 2 2.5 3 3.5 4 a circuit-level method is presented, both through experiments time (s) and simulations, to provide a solution to the device-level (a) problem of the temporal variability that still affects the com- 200 mercialization of the ReRAM-based memories. The proposed Cumulative Sample No. scheme can be conveniently adopted by ReRAM arrays with 150 a single noise generator circuit in array’s periphery, shared w/o Noise 100 w/ Noise row/column-wise throughout the array during the writing 50 process. The next immediate steps of this work comprise 0 addressing of potential implementation constrains of noise 0 10 20 R 30 /R 40 50 60 scheme, enhancement of the proposed scheme using optimized OFF ON pulse width, and in-depth experimental investigation. (b) Fig. 7. (a) Applied voltage and measured current during a W1 − R1 − W0 − R0 cycle. The blue lines show a case without noise and the orange R EFERENCES lines represent one stochastic realization of the noisy cases. (b) Cumulative [1] D. E. O’Leary, “Artificial Intelligence and Big Data,” IEEE Intelligent distribution function plot of the ROF F /RON ratio without (blue) and with Systems, vol. 28, no. 2, pp. 96–99, 2013. (orange) additive input noise. [2] S. Yu and P.-Y. Chen, “Emerging Memory Technologies: Recent Trends and Prospects,” IEEE Solid-State Circuits Magazine, vol. 8, no. 2, pp. programming cycles, half of them without noise and the rest 43–56, 2016. with additive noise during the writing pulses. Restricted by [3] IEEE. (2018) IRDS™ 2018: Beyond CMOS. [Online]. Available: https://irds.ieee.org/home/what-is-beyond-cmos the sampling capabilities of the instrumentation, long-width [4] A. Chen and M.-R. Lin, “Variability of resistive switching memories (1s) and low-voltage (±1.2V) writing pulses are applied, as and its impact on crossbar array performance,” in 2011 Int. Reliability well as, for the noisy cases, while the additive noise is Physics Symp. IEEE, 2011, pp. MY–7. [5] P. Pouyan, E. Amat, S. Hamdioui, and A. Rubio, “Resistive Random produced by zero-mean Gaussian process through Matlab with Access Memory Variability and Its Mitigation Schemes,” Journal of Low σ = 75mV and sampling time ≈ 10ms. As a figure of merit, Power Electronics, vol. 13, no. 1, pp. 124–134, 2017. the ROF F /RON ratio is calculated for every single program- [6] M. Pedro et al., “Device variability tolerance of a rram-based self- organizing neuromorphic system,” 2018 IEEE Int. Reliability Physics ming cycle using the values of the measured current during Symp., pp. P–CR.4–1–P–CR.4–5, 2018. the reading pulses. The cumulative distribution functions are [7] L. Gammaitoni, P. Hänggi, P. Jung, and F. Marchesoni, “Stochastic illustrated in Fig. 7(b), where the blue line represents the part Resonance,” Reviews of modern physics, vol. 70, no. 1, p. 223, 1998. [8] A. Stotland and M. Di Ventra, “Stochastic memory: Memory enhance- without noise and the orange line the results of the noisy part. ment due to noise,” Physical Review E, vol. 85, no. 1, p. 011116, 2012. It is evident that noise-induced programming achieves a higher [9] V. Ntinas, A. Rubio, G. C. Sirakoulis, and S. D. Cotofana, “A Pragmatic ratio. A complementary in-depth investigation of experimental Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement,” in 2019 IEEE Int. Symp. on Circuits and Systems, 2019. part is subject to further on-going research, aiming to enhance [10] A. Ascoli, F. Corinto, V. Senger, and R. Tetzlaff, “Memristor Model method’s application to ReRAM crossbar arrays. Comparison,” IEEE Circuits and Systems Magazine, vol. 13, no. 2, pp. 89–105, 2013. [11] M. Pedro, J. Martin-Martinez, R. Rodriguez, M. Gonzalez, F. Cam- VI. C ONCLUSIONS pabadal, and M. Nafria, “A flexible characterization methodology of rram: Application to the modeling of the conductivity changes as In this work, the Bit Error Rate (BER) of a ReRAM-based synaptic weight updates,” Solid-State Electronics, vol. 159, pp. 57 – memory cell is explored and a power-efficient method based 62, 2019. [12] H. Li, P. Huang, B. Gao, B. Chen, X. Liu, and J. Kang, “A SPICE on the Stochastic Resonance (SR) phenomenon is proposed Model of Resistive Random Access Memory for Large-Scale Memory for BER reduction. More specifically, ReRAM devices exhibit Array Simulation,” IEEE Elect. Dev. Let., vol. 35, no. 2, pp. 211–213, inherent stochastic switching that results in the high BER 2014. [13] H. Li, P. Huang, B. Gao, X. Liu, J. Kang, and H.-S. P. Wong, “Device of ReRAM-based cells. Aiming to tackle this issue, a noise- and circuit interaction analysis of stochastic behaviors in cross-point induced method for the successful writing of ReRAM-based rram arrays,” IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 4928– cells is proposed, where additive white Gaussian noise is 4936, 2017. [14] H. Li et al., “Variation-aware, reliability-emphasized design and opti- integrated to the writing pulses, following the principles of mization of rram using spice model,” in 2015 Design, Automation Test SR. Even though the external additive noise can be considered in Europe Conf. Exhibition, 2015, pp. 1425–1430. as nuisance, the performance of the system, evaluated by [15] V. Ntinas et al., “Noise-induced performance enhancement of variability- aware memristor networks,” in 2019 26th IEEE Int. Conf. on Electronics, the BER, is subject to improvement for a specific range Circuits and Systems. IEEE, 2019, pp. 731–734. of the noise intensity. Moreover, the proposed method is [16] A. Grossi et al., “Impact of Intercell and Intracell Variability on Forming compared with the amplification of the writing pulses without and Switching Parameters in RRAM Arrays,” IEEE Trans. Electron Devices, vol. 62, no. 8, pp. 2502–2509, 2015. the presence of additive noise, which can also achieve BER