Two-dimensional materials prospects for non-volatile spintronic memories

Non-volatile magnetic random-access memories (MRAMs), such as spin-transfer torque MRAM and next-generation spin–orbit torque MRAM, are emerging as key to enabling low-power technologies, which are expected to spread over large markets from embedded memories to the Internet of Things. Concurrently, the development and performances of devices based on two-dimensional van der Waals heterostructures bring ultracompact multilayer compounds with unprecedented material-engineering capabilities. Here we provide an overview of the current developments and challenges in regard to MRAM, and then outline the opportunities that can arise by incorporating two-dimensional material technologies. We highlight the fundamental properties of atomically smooth interfaces, the reduced material intermixing, the crystal symmetries and the proximity effects as the key drivers for possible disruptive improvements for MRAM at advanced technology nodes. Developments, challenges and opportunities in using two-dimensional materials for the next generation of non-volatile spin-based memory technologies are reviewed, and possible disruptive improvements are discussed.

Non-volatile magnetic random-access memories (MRAMs), such as spin-transfer torque MRAM and next-generation spin-orbit torque MRAM, are emerging as key to enabling low-power technologies, which are expected to spread over large markets from embedded memories to the Internet of Things. Concurrently, the development and performances of devices based on two-dimensional van der Waals heterostructures bring ultracompact multilayer compounds with unprecedented material-engineering capabilities. Here we provide an overview of the current developments and challenges in regard to MRAM, and then outline the opportunities that can arise by incorporating two-dimensional material technologies. We highlight the fundamental properties of atomically smooth interfaces, the reduced material intermixing, the crystal symmetries and the proximity effects as the key drivers for possible disruptive improvements for MRAM at advanced technology nodes.
Emerging technologies generally follow a hype cycle before reaching the mature production stage. When NAND flash memory was first commercialized in 1989, it competed against conventional non-volatile memories such as electrically erasable programmable read-only memory 1 . Even when its market size reached over US$1.8 billion in 1995, the semiconductor industry was still uncertain about the full potential of this technology. However, new applications such as MP3 players and smart phones, which rapidly increased end-use demands, fuelled NAND flash development to reduce the cost per bit, resulting in three-dimensional (3D) NAND flash innovation 2 . Mobility and miniaturization trends in consumer electronics have continuously driven the NAND flash market, which reached over US$50 billion in 2020 3 . In contrast, although the potential of spintronic memories in terms of low power and speed is proven, they are still emerging in terms of market size. The most advanced emerging generation of magnetic random-access memory (MRAM), based on the spin-transfer-torque mechanism (Fig. 1), is already addressing a few market segments. However, it is envisioned that, in the near future, the MRAM market will expand significantly by addressing the power and data-transfer (memory-wall bottleneck) challenges in a variety of embedded applications, including neural networks and in-memory computing 4,5 . Considering that the embedded emerging non-volatile memory market is forecasted to grow from US$20 million in 2019 to US$2.5 billion by 2025 6 , it could well drive MRAM growth, like mobile consumer electronics has driven NAND flash growth in the past. To achieve such growth, MRAM technology must meet a variety of challenges that require material and device integration breakthroughs, in which two-dimensional materials (2DMs) could play a key role.
Indeed, since the discovery of graphene, followed by an ever-growing family of related materials 7 , 2DMs have emerged as potential enablers for potentially ultracompact device architectures or radically new concepts for spin information processing 8,9 . Scientific advances of 2DM-based spintronic devices, as well as recent progress in large-scale co-integration of 2DMs with conventional microelectronics materials 10,11 , have opened a promising perspective for developing innovative MRAM technology.
Here we provide an overview of the most recent developments, identify challenges and opportunities brought by 2DMs for MRAM, and give a vision of how progress in 2DMs research could morph into a game-changing solution for future generations of spintronic-memory technologies. We first describe fundamental MRAM concepts and the prospects for MRAM commercialization, including the main roadblocks for broader deployment. We then highlight the unique opportunities brought by 2DMs and van der Waals (vdW) heterostructures to overcome some of the technological challenges. Afterwards, we analyse the requirements and challenges for further advances concerning growth, processing and integration of 2DMs to enable an impact in next-generation spintronic-memory development. Finally, an outlook provides a vision of 2DM-MRAM technologies. on electrically generated spin currents have emerged to control the FL magnetization: spin-transfer torque (STT) 12 and spin-orbit torque (SOT) 13 .
The STT concept was first introduced in 1996 14,15 and implemented at STT-MRAM chip level in 2005 16 . STT is observed in a two-terminal geometry, in which a vertical current is injected through the MTJ (Fig. 1a). The current tunnelling through the barrier is spin-polarized, leading to the FL magnetization reversal for large enough currents, owing to the transfer of angular momentum. The relative magnetization orientation of the FL and RL layers determines the resistance of the device, which is monitored by the tunnelling magnetoresistance (TMR).
SOT-MRAM is based on three-terminal devices, where an additional conducting path is added adjacent to the FL (Fig. 1b). A charge current flowing through this path results in the injection of a spin-polarized current into the FL in virtue of the spin-Hall and/or Rashba-Edelstein effect 13,[17][18][19] . In such devices, SOT can switch the FL magnetization without passing a current through the MTJ tunnel barrier. At the expense of adding another terminal, the decoupling of the write and read current paths prevents write errors during read operation and reduces the risk of voltage breakdown. It further enables versatile cell designs by allowing the spin torque direction to be set independently of the anisotropy direction in the stack 20 . Using SOT, magnetization switching has been observed on the picosecond timescale 21 .

Commercialization and challenges of spin memory
Successful commercialization of STT-MRAM in solid-state drives and wearable electronics (Box 1) has been achieved after several major breakthroughs in MTJ technologies 22 , including enhanced STT-switching efficiency and TMR amplitude, interfacial perpendicular magnetic anisotropy (PMA) at magnetic metal/oxide interfaces [23][24][25] , synthetic antiferromagnets (SAFs), the suppression of etch-induced sidewall re-deposition and a reduction in process variability (Fig. 2). To cover a broader range of envisioned applications (Box 1), further development of cost-effective and versatile MRAM technology will be crucial. It will also be necessary to ensure proper downscaling to maintain competitiveness at advanced technology nodes, in particular regarding MTJ diameter and cell-to-cell pitch. For example, because of the required analogue circuitry, as a rule of thumb it is desirable to keep the STT-MRAM bit cell about three-times smaller than the static random-access memory (SRAM) cell size at a given technology node so that the benefit is worth the technology change.
Improving the MTJ stacks and their versatility using conventional materials and integration processes is a difficult challenge. The actual stacks consist of dozens of ultrathin layers ( Fig. 1) in which each material and interface plays an important role in determining the device performance (Fig. 2). Below, we discuss some of these important aspects. In terms of materials, modern MRAMs rely on the crystalline magnesium oxide (MgO) tunnel barrier, whereas the FM layers that are in contact with MgO are typically made of crystalline cobalt-iron-boron (CoFeB; Fig. 2a). The CoFeB/MgO/CoFeB combination is attractive because of its high TMR ratio originating from the spin filtering effect in crystalline MgO/FM, as predicted in 2001 26 (Fig. 2b). The structure appears to be simple but practical devices are far more complex. The RL layer requires a much higher magnetic anisotropy than the FL to be stable during memory operation. For this purpose, almost all MRAMs use a multilayer SAF to pin the RL (Fig. 2c), which relies on strong antiferromagnetic coupling between two ferromagnetic layers, and gives rise to a magnetically hard structure.
Another crucial point is PMA [23][24][25] (Fig. 2d) because perpendicularly magnetized stacks have a better scalability than the in-plane magnetized counterparts. Owing to the switching dynamics induced by STT, a better trade-off between the thermal stability of the FL magnetization and the write current is obtained in out-of-plane magnetized MTJs 27 . Interfacial PMA can originate from spin-orbit interactions deriving from electronic hybridization effects, magnetocrystalline anisotropy and interfacial strain. PMA was demonstrated in a tantalum (Ta)/ CoFeB/MgO structure 24 but requires very thin CoFeB, which results in increased damping from the spin pumping effect and less efficient STT, whereas the anisotropy strength is insufficient for small devices (less than 30 nm). A solution for these issues involves double MgO barriers, such as MgO/CoFeB/MgO and MgO/CoFeB/Ta/CoFeB/MgO (Fig. 2d). Here, having the FL between two oxide barriers effectively increases the anisotropy 28,29 , providing thermal stability of the magnetization down to about 20-nm cell diameter 30 . Other approaches to enhance PMA below 20 nm rely on vertical shape anisotropy 31,32 , but these concepts face manufacturing challenges owing to the large MTJ aspect ratio.
As the MTJ size is downscaled, the TMR must remain high enough, whereas an increase in the PMA is required to maintain thermal stability and data retention. However, the enhanced anisotropy of these structures forces the use of large current densities to achieve reliable magnetization switching, which increases energy consumption. As such, introducing voltage controlled magnetic anisotropy (VCMA) to assist or induce the switching could be helpful (Fig. 2e). It has been shown that a voltage across the MgO tunnel barrier results in charge accumulation near the FL/MgO interface, inducing atomic-orbital occupancy changes that modulate the magnetic anisotropy [33][34][35] . VCMA-assisted writing could therefore reduce the energy dissipation and memory cell area by lowering the driving current. Unfortunately, the strength of the VCMA effect in CoFeB/MgO remains insufficient for practical implementations.
Pitch scaling also tends to increase the failure rate by forming shunting paths on the sidewall owing to metallic re-deposition during MTJ patterning 36 . The physical and chemical damages on the pillar sidewall become even more problematic for downscaled MTJ devices. Broken symmetry of atomic bonding on the sidewall from physical bombardment or chemical diffusion of etching gases significantly degrades both the spin polarization and the magnetic anisotropy. Finally, another important issue is related to atomic intermixing at interfaces, taking place between the metallic layers in the MTJ during the post thermal annealing at about 400 °C required to improve the MTJ crystallinity and complementary metal-oxide-semiconductor (CMOS) integration (Fig. 2f). When intermixing reaches the tunnel barrier, it leads to performance deterioration. This issue becomes more relevant as the thickness of the layers is reduced at advanced nodes, as the risk of failure of the tunnel barrier increases when the layer roughness becomes comparable to its thickness. There are also various integration and material challenges associated with SOT-MRAM (Fig. 2g). SOT-MRAM uses the technological platform of STT-MRAM, thus knowledge and solutions developed for STT-MRAM could be transferable to SOT-MRAM development. However, a fundamental difference lies in the stack design. Whereas in STT-MRAM the FL generally is on the top of the MTJ stack (bottom pinned; Fig. 1c), in SOT-MRAM, it is on the bottom (top pinned; Fig. 1d). This forces a re-design of the material growth protocols and the introduction of specific seed layers to achieve the desired crystallinity of MTJs. Stacks with in-plane magnetization increase the SOT cell size, although they have the benefit of magnetic field-free switching. In contrast, for deterministic switching of perpendicular anisotropy SOT devices, an in-plane external magnetic field along the current direction is required (Fig. 2g). This magnetic field is a major hurdle for practical SOT-MRAM applications. Various solutions have been proposed to obtain field-free switching, such as complex shapes 37,38 , the use of an in-plane MTJ 39 that limits scalability and speed, the insertion of an in-plane magnet below the SOT line increasing writing currents 40 , or using antiferromagnetic heavy-metal SOT lines 41 . Although the embedding of a magnet in a 12-inch wafer integration process has been demonstrated 42 , this solution comes at the expense of uniformity, cost, security and MTJ stability.

Opportunities with 2DMs for MRAM
Major progress in spin-torque memory technologies has been achieved by material developments. However, so far, only a limited number of optimal material combinations have been identified; in particular, CoFeB/MgO has played a prominent role for nearly two decades as no alternative has been found yet. Consequently, MRAM technology faces severe constraints, threatening its future evolution and broad deployment. In recent years, wide varieties of novel emerging 2DMs and heterostructures have shown the potential to address the aforementioned issues and challenges. In a monolayer form, 2DMs are atomically thin and their interfaces are atomically smooth. They interact weakly, through vdW interaction, with minimal element intermixing. In addition, given their atomically thin nature, their properties could be tuned by external electric fields or proximity effects 9 . They exist in metallic, insulating, semiconducting, ferromagnetic and antiferromagnetic forms without or with broken crystalline symmetries, and presumably, they can be stacked in any preferred combination and order. Therefore, the properties and versatility of 2DMs make them very attractive for spintronics and, in particular, for memory technologies, which strongly rely on ultrathin materials and their interfaces Box 1

MRAM markets and commercialization
STT-MRAM is the only non-volatile memory capable of high-density, high-endurance and fast-write operation and is considered as the best candidate for embedded non-volatile applications. The microcontroller units (MCUs) market in 2020 was over US$25 billion and will be driven by 5G IoT, wearable, general-purpose MCUs and automotive electronics 201 . STT-MRAM can replace SRAM and NOR flash in low-power MCUs, decreasing cost and power consumption. STT-MRAM is also promising for memory replacement in the automotive and biosensor sectors. There, embedded flash (eFlash) is either not available or less cost-effective than embedded MRAM beyond the 28-nm node. SOT-MRAM is under development and its applications would be primarily as SRAM cache-memory replacement from L3/L4 to L2/L1 cache levels and registers in central processing units and graphical processing units. SOT-MRAM also has potential in non-volatile logic elements 202,203 and for in-memory computing 204 .
STT-MRAM has been released down to 28 nm, where eFlash technology co-exists. However, eFlash scaling is reaching its limits, while SRAM scaling becomes challenging owing to stand-by leakage currents 205 . Applications include enterprise solid-state drives, storage-class memory and wearable electronics. In 2017, Everspin shipped standalone 256-Mb STT-MRAM using GLOBALFOUNDRIES 40-nm technology 206 and started the production of 1-Gb STT-MRAM at the 28-nm node 207 . Taiwan Semiconductor Manufacturing Company has also developed a 22-nm technology, whereas Samsung Foundry commercialized in 2019 an embedded STT-MRAM macro built on a low-power 28-nm fully depleted silicon-on-insulator platform 208 (Fig. 4). GLOBALFOUNDRIES has also delivered embedded STT-MRAM on its 22-nm fully depleted silicon-on-insulator platform for IoT and automotive applications 209 . Embedded STT-MRAM is expected to expand in low-power wearable and radiofrequency applications, as demonstrated by Intel 210 .
Potential markets. MRAM is considered as the only non-volatile memory with high-density, endurance and fast writing speed. Applications can be divided into three different categories: low-bandwidth (BW) non-volatile random-access memories (NVRAM), high-BW NVRAM and NOR flash replacement. The MRAM memory cell is formed at the BEOL without disturbing pre-established front-end processes (Fig. 1), which simplifies its implementation across multiple technology nodes. AIoT, artificial intelligence of things; CPU, central processing unit; SCM, storage class memory.  Owing to their atomically thin nature, 2DMs enable enhanced tunability of their properties, including gating and proximity effects. f, Intermixing and interface roughness become critical when scaling requires very thin (less than 1 nm) tunnel barriers. This results in tunnelbarrier performance degradation and a lack of reproducibility, which can be circumvented with atomically smooth 2DMs and 2DM diffusion barriers. g, For perpendicularly magnetized MTJs, an in-plane external magnetic field (H) along the current (I) direction is typically required for switching. Low-symmetry 2DMs could help to eliminate the need for such a magnetic field. T || and T ⊥ are the in-plane and out-of-plane oriented torque, respectively.
to harness the required functionalities (Fig. 2). Although 2DM-based technologies are far from reaching the level of maturity of MgO/ CoFeB-based MTJs (for example, the first 2D magnets were isolated in a monolayer form just a few years ago and are at present barely exceeding room-temperature operation) [43][44][45][46] , vdW heterostructures are taking an increasingly prominent role in spintronics research.

Interfacial PMA and synthetic antiferromagnets
As the MTJ size scales down, the energy barrier to switch the FL decreases, which in turn increases its bit-to-bit variation, hence degrading data retention 47 . In principle, intrinsic interfacial PMA (Fig. 2d) can be enhanced by using FM materials with large spin-orbit coupling 23 . However, the use of an amorphous FM alloy is preferred to achieve epitaxial crystallization of the MgO barrier upon annealing 48 , which constrains the selection of the FM material. Besides, increasing the spin-orbit coupling in the FL would increase the damping and the write current 23 . Accordingly, there is a crucial need for innovative material alternatives to enable STT-MRAM below 15-20 nm. In this context, 2DMs have been investigated as promoters of large PMA. The combination of graphene with Co, Fe and/or iron-palladium (FePd) has shown promising results [49][50][51][52][53][54] . For example, calculations show that the PMA of Co films coated by graphene (on one or both surfaces) is enhanced by up to 100% compared with the PMA of pure Co, reaching an upper value of about 2 mJ m −2 (ref. 51 ). The critical thickness of Co at which the out-of-plane to in-plane magnetization transition occurs (>13 monolayers (ML) or >2.6 nm) increases, as confirmed experimentally with graphene/Co/Ir(111) samples [50][51][52] (Fig. 2d). In comparison, the PMA of pure Co vanishes beyond 7 ML. Downscaling potential to a MTJ pillar diameter of 10 nm has been estimated when both Co surfaces are covered by graphene or for FePd/graphene interfaces 55 (Fig. 2d). Interestingly, graphene also presents potential for implementing SAFs, as revealed by the strong antiferromagnetic exchange coupling across a graphene spacer in out-of-plane magnetized FM/graphene/ FM structures (Fig. 2c) 51,53,56 . The integration of graphene-based FL in STT/SOT-MRAM could minimize the Dzyaloshinskii-Moriya interaction arising at Co/graphene interfaces 57 , which has a detrimental effect on device switching performance 58-61 .

Encapsulation and intermixing suppression
As the lateral dimension of MTJs shrinks, device morphology profiles become very rough and non-uniform. Chemical-vapour-based 2DMs embedded in the MTJs can help overcome fabrication challenges and improve the device morphology as the tunnel barrier thickness and lateral dimension downscale (Fig. 2). Their atomically thin, flexible and generally inert nature can minimize defects related to dangling bonds, interface states and interfacial alloy formation 62 . For example, graphene can be simultaneously used as a contact and heat dissipation layer and hexagonal boron nitride (hBN) as an encapsulation and insulating layer.
2DMs can suppress the diffusion of atoms in MTJs. Intermixing reaching the tunnel barrier eventually leads to device performance deterioration. Graphene and hBN have a dense electron cloud structure and a low chemical reactivity owing to their compact hexagonal honeycomb lattice, making it difficult for even the smallest helium atom to spread. For this reason, 2DMs have been heralded as atomically thin impermeable membranes 63,64 to prevent the oxidation and corrosion of metals 65,66 and allow novel processes for spintronics such as atomic layer deposition (ALD) 67,68 . Large-area 2DMs uniformly grown by chemical vapour deposition (CVD) can therefore be used as an encapsulating layer to protect patterned MTJ cells from the post thermal and interdiffusion of back-end-of-line (BEOL) processes (Fig. 2f). Similarly, many organic materials (as used in organic light-emitting diodes, for instance) hold tailoring potential for spintronics 69 , which 2DMs integration could unleash by stabilizing interfaces.
Thickness engineering of material spacers follows a trade-off relationship 25,70,71 . A thick spacer could provide suitable texture decoupling and a diffusion barrier, but the magnetic coupling weakens. 2DMs could provide ideal spacers as the trade-off relationship can be efficiently optimized. Large-scale 2DMs grown by CVD on FMs 72-74 preserve interfaces with spin-polarized metallic states even after exposure to oxidative conditions 67,68,75,76 . Graphene and hBN have shown outstanding performance as atomic diffusion barriers down to the monolayer 68,77,78 . Notably, large-scale graphene growth on high-magnetocrystalline-anisotropy and low-magnetic-damping FePd L1 0 PMA-ordered alloy was recently achieved 54 .
It is important to note that theoretical ab initio studies on CoFe/ MgO/CoFe-based MTJs have predicted TMRs 26 in the range of several 1,000% whereas experimentally the room-temperature record is 604% and the TMR in commercial products is about 200% (refs. 116,117 ). This discrepancy is due to defects in the MgO tunnel barrier, lattice mismatch between MgO and FM, diffusion of boron or other elements towards the MgO barrier, and so on. With 2DMs, the MTJ stack could be closer to the ideal one owing to their high stability, suppressed diffusion and well defined interfaces, which would favour downscaling. For example, all-2D-based MTJs comprising a 2D tunnel barrier and 2D magnetic layers could be envisioned (Fig. 2f). A TMR of 160% at low temperature has been reported in an MTJ entirely made of 2DMs (Fe 3 GeTe 2 /hBN/Fe 3 GeTe 2 ), with PMA and a spin polarization exceeding 60% gate tunability 100 . A larger TMR was predicted in Fe 3 GeTe 2 -based MTJs for various vdW spacers 118 .
Furthermore, the fact that 2DMs and their heterostructures are atomically thin promises less technological efforts to process them into functional devices, avoiding technological steps such as planarization. They could further enable novel memory elements as alternatives to traditional MTJs (Fig. 2b). A low-temperature magnetoresistance as large as 19,000% was observed in tunnel junctions of four-layer CrI 3 , a layered insulating antiferromagnet 119,120 , whereas a TMR up to 100,000% was predicted for vanadium diselenide 121 .

Spin-orbit torques
Compared with SRAM, the stand-by power of SOT-MRAM is negligible, but projected write (<75 fJ) and read (<25 fJ) energies using state-of-art stacks must be reduced 122 . Reading is directly linked to the minimum current detectable by the sense amplifiers and stand-by power. For fast reading of <5 ns with about 150−200% TMR, the read current should be about 50−80 µA. Typical transistor current capabilities in sub-28-nm technology nodes with minimum footprint is on the order of 30-100 µA, whereas state-of-the-art perpendicular SOT-MRAM projects a critical write current of about 300 µA per bit cell 122,123 . Hence, to prevent CMOS from dominating the cell size, a straightforward way is to improve the SOT efficiency ξ, the conversion ratio between spin and charge currents, to ξ > 1, whereas heavy-metal layers, such as platinum (Pt) and tungsten (W), yield ξ = 0. 1-0.5 (refs. 123-125 ).
The integration of 2DMs provides appealing opportunities for SOT-MRAM. The large spin-orbit coupling and associated spin textures of 2DMs, including TMDCs and topological insulators, make them serious candidates for inducing large spin torques. The most studied topological insulators are the Bi 2 Se 3 and the (Bi 1-x Sb x ) 2 Te 3 families of materials. The observation of large damping-like torques and the achievement of room-temperature magnetization switching confirms their potential for SOT-MRAM 126,127 . Owing to the reduced crystal symmetry of some TMDCs, unconventional torque components are also expected. Of significant relevance, an out-of-plane damping-like torque can be induced by WTe 2 and niobium diselenide 128,129 (Fig. 2g), which could enable field-free SOT switching in perpendicular SOT-MRAM. A pronounced SOT is expected not only from the bulk but also from the surface in topological Weyl semimetals. Roomtemperature magnetization switching in a regime of domain wall motion has been reported in WTe 2 /permalloy (Py) and WTe x /Mo/CoFeB heterostructures 128,130,131 .

Engineering and tuning material properties
The control of the magnetic anisotropy with electric fields (VCMA) provides an engineering knob to optimize the trade-off between data retention and writability as well as to reduce the energy consumption. In current MTJs using metalling FMs, electric fields only penetrate a few ångströms into the film surface, limiting the efficiency to control the magnetic properties. In contrast, the 2D magnets' magnetic properties, Curie temperature, magnetic anisotropy and spin filtering through MgO are largely tunable using external stimuli such as electric fields 88 , strain [140][141][142][143] or light.
Another exciting aspect is to leverage the asset of hybridization (proximity or interface effect) 9,69,93,144 that could allow spin filtering and resistance-area product reduction (to less than ohms per square micrometre). It has already been shown that in proximity to an FM, the large-gap, insulating hBN becomes metallic, leading to spin filtering and a TMR of 50% in a 2D-MTJ 77 . Similarly, for graphene, it is possible to reach a TMR of 80% (ref. 78 ). Other 2DMs such as TMDCs (with specific thickness-dependent band-structure mechanisms) are now being explored to further tailor spin selection at FM interfaces 102 . Finally, graphene can further increase the current at the boundary between a large spin-orbit coupling material and the FM. Room-temperature, proximity-induced spin-orbit coupling effects, which are tunable by gating, have been recently observed in graphene/WS 2 (ref. 145 ). In combination with the proximity-induced effect, an enhanced spin torque could be obtained.

Material and integration challenges
Material challenges MRAM is expected to progressively become mainstream in rapidly expanding areas such as the Internet of Things (IoT) and artificialintelligence-based devices (Box 1), for which the development of cost-effective, downscaled MRAM technology will be essential 146 . However, the limited portfolio of the available state-of-the-art 3D materials and architectures could become an unsurmountable obstacle for the industry. In this regard, 2DMs offer unique opportunities; to advance their use, several notable challenges lie ahead that require material research and development, in hand with engineering efforts 147,148 .
There are thousands of predicted stable 2DMs, including insulators, semimetals, magnets and novel electronic phases, such as Weyl semimetals or topological insulators [149][150][151] . Many have properties that make them potentially attractive for magnetic memory technologies. Substantial attention must therefore be directed towards identifying and characterizing the most promising candidates to optimize MRAM performance. MTJs incorporating 2DM tunnel barriers 93 currently show TMR values 78 that are already comparable to those of the first generation of crystalline MgO barriers 152 that later became technologically relevant devices 116,117 . This is reinforced by the added potential of the newly developed 2D magnets 153 . Although we cannot predict whether such a suitable 2DM for memories will be available anytime soon, we can highlight the tremendous efforts by the community in this direction [43][44][45][46] . For instance, considering that the first 2D magnets were reported in 2017 86,87 , already observing 2D magnets with Curie temperatures near room temperature is impressive, and efforts are underway to achieve this beyond room temperature, relying on new material sets, improved control and sample quality, and doping approaches [154][155][156][157][158][159] . Hence, although the results are not yet competitive for present-day room-temperature standards, the effort made by the community and the fast pace of progress made in the recent years (from tunnel barriers to 2D magnets) to target functional large-scale, spin-based technologies allow us to foresee the possibility of functional large-scale, spin-based technologies operating at room temperature in the not so distant future.
Reported SOT efficiencies with 2DMs, especially topological insulators, largely surpass those of heavy metals. Crystal-dependent symmetries for field-free switching and VCMA are phenomena not easily implemented in present-day MRAM materials. However, most SOT studies use micrometre-scale devices, where magnetization switching may occur via mechanisms with low activation barriers, such as domain motion. Future research efforts are required to extend these studies to practical sub-100-nm devices. In hybrid systems, the reactivity between 3D transition metals and 2D chalcogenides changes the nature of the interface, which may form uncontrolled interfaces owing to chemical reaction [160][161][162][163] . Alloys and magnetic dead layers can modify the underlying SOT mechanisms 162,163 . However, if mastered, hybridization could become an asset for moving towards ultracompact geometries 69,162 . An all-2D vdW heterostructure (Fig. 3d) would provide an opportunity to control SOT phenomena and may help overcome diffusion issues.
Explorative experiments with 2DMs are typically carried out using micrometre-sized flakes exfoliated mechanically from bulk materials. This technique is not up-scalable. The development of a 12-inch wafer-scale CMOS-compatible growth process (direct growth on process wafer or layer transfer; Fig. 3a) is thus necessary to address the scalability issue; this remains a critical challenge for any 2DM implementation in microelectronics 147,148 . Furthermore, follow-up integration processes will need to maintain the original structure and device performance of 2DMs (delamination risk elimination, 90   The projected feature size of the MTJ is shown at the top of the chart, together with the technology node at which a given MTJ size would be introduced. STT-MRAM offers non-volatility together with low power consumption, which is ideal for low-power MCUs, wearables and IoT applications (Box 1). In terms of embedded non-volatile memory (eNVM) technology, eFlash scaling will probably reach its end at the 28 nm/22 nm node. STT-MRAM is also promising for automotive and SRAM replacement. Chipmakers and foundries started mass production for eFlash-type STT-MRAM in 2018 and started to develop SRAM-type applications for cache. SOT-MRAM can address high-speed and high-endurance applications such as cache and in-memory computing. The memory speed is best characterized by the latency time, which includes electrical time delays induced by routing from selector control to memory points and associated parasitic resistances and capacitances. As the memory size increases, the speed tends to decrease. Current MRAM technologies based on bulk materials are expected to reach their limits at about 20-nm MTJ feature size, after which 2DMs could play a key role to maintain MRAM downscaling. Actual 2DM milestones are shown at the bottom of the chart, including recent demonstrations of magnetization switching in heterostructures comprising 2DM-SOT materials and/or 2D-FMs. Enabling 2DM-based technologies are indicated with STT and SOT technology projections and should be introduced at the indicated timelines to offset today's MRAM materials limitations. Efforts such as the European Union 2D Experimental Pilot Line are expected to accelerate the path to production 198 . IP, in-plane; Perp, perpendicular; GPC, general purpose computer; TSMC, Taiwan Semiconductor Manufacturing Company; e-DRAM, embedded DRAM; HPC, high-performance computing. The yellow shaded region indicates the technology advances from STT to STT/SOT. surface treatments and low damage co-integration with MRAM stacks; Fig. 3b,c).

Large-scale growth
Growth methods to obtain uniform 2D layers on large areas could be based either on chemical methods (for example, CVD) or on physical deposition such as MBE, PLD and sputtering 114,115,147,[164][165][166][167][168][169][170][171] (Fig. 3a). Chemical routes are arguably the most promising owing to their low cost and compatibility with large-wafer processing but progress so far is limited to a few selected materials. Single-crystal growth of graphene and hBN has been scaled beyond 6-inch wafer at over 1,000 °C using CVD [172][173][174] and although single-crystal growth remains to be achieved, polycrystalline graphene growth has been demonstrated at 450 °C with plasma CVD 175,176 . During CVD growth, precursors react in the vapour phase in the wafer surface (650−1,000 °C). A low nucleation rate leads to the formation of large isolated flakes of high crystalline quality, which cover only a small fraction of the substrate, with randomly oriented domains and poor control of the number of layers. The use of less stable metal and chalcogen precursors in TMDC growth reduces the growth temperature (300−560 °C) and increases the nucleation rate [177][178][179] . Precursor control growth could drastically reduce the thermal budget for the fabrication, which is a promising approach for direct growth in BEOL-compatible wafers. Using this technique, monolayers of TMDCs are grown over a wafer scale, but they remain polycrystalline, which degrades their electrical properties.

Processing and integration
After the growth over large areas of high-crystalline-quality 2DMs, their transfer from the growth to the target substrate is required for further processing and device integration (Fig. 3b). In this respect, the technological challenge consists of maintaining the 2D layer integrity during the process. The most widely used approach is the polymer-assisted transfer, in which a polymer film is used to mechanically support the 2DM [180][181][182] . The release from the growth substrate could be achieved in a solution by electrochemistry, chemical dissolution of the substrate, or simply intercalation of water between the substrate and 2DM. Recently, another transfer method called spalling has been developed, where the 2DM is detached from the substrate by the strain induced by a metallic film grown onto it 183,184 . The metal/2DM stack is then transferred onto the target substrate and the metallic film is chemically etched.
Although 2DMs are generally compatible with standard integration processes such as photolithography, etch and deposition, significant process optimization would still be needed to maintain the original structure and properties of the 2DMs. Of particular relevance are reducing damage in plasma-based processes, increasing adhesion and suppressing material lifting in chemical processes, and patterning by etching in combination with selective stop techniques [185][186][187][188][189] . Another point of attention is to retain the original structure of 2DMs without self-deformation, degradation and interference with other layers. For instance, the deposition of a conventional MRAM stack is carried out using sputtering, which can expose the 2DM seed to a plasma that can easily damage the 2DM. Some solutions have been proved viable (off-axis, flipped chip) 190 and have to be adapted to large-scale tools, such that the deposition condition can be modified to be damage free (see Fig. 3c as an example) while not degrading magnetic properties and stack performances.

Outlook and roadmap
Today, a variety of memory technologies complement each other for computing, data storage and embedded applications. Figure 4 outlines a roadmap for MRAM. STT-MRAM has been already commercialized for persistent memory in storage devices and servers as well as wearable electronics. MRAM is fostering key emerging markets, such as wearable, automobile, IoT, biosensor, various cache and buffer memory applications. Its development over recent years has been astonishing and it is clear that it will shortly play a central role in the embedded non-volatile memory market.
However, the requirements of each application vary significantly, as summarized in Table 1. Flash-replacement STT-MRAM requires high data retention (>20 years) but accepts low endurance (10 6 cycles). In contrast, SRAM-replacement STT-MRAM requires high endurance (>10 12 cycles) and high bandwidth but needs much less data retention, even down to a few seconds. One major challenge for automotive applications is reliable chip operation even under extreme environments such as a high temperature of 150 °C or exposure to external magnetic fields that can increase the bit error rate. Good read margin up to 150 °C and magnetic immunity to guarantee 10 years reliability have been demonstrated 47,191,192 . Finally, both bit-cell size reduction and operation speed enhancement are key factors to expand into the SRAM-replacement area. Recently, a write/read speed less than 10 ns and 10 12 cycling endurance was demonstrated 193 showing promise for SRAM replacement. In contrast, SOT-MRAM is still a topic of intense research and under industrial initial assessment [123][124][125] . To move forward, the first step is to establish the manufacturability using industrial CMOS-compatible processes. In fact, SOT-MRAM was recently demonstrated up to 12-inch scales 42,123 with reliable subnanosecond switching, low error rates and high endurance on Ta/CoFeB/MgO or W/CoFeB/MgO stacks using either perpendicular 42,[194][195][196] or in-plane 39,197 magnetization.
It is, however, unknown how scaling beyond the 14-nm node will be achieved with conventional materials, when the MTJ feature size is projected to be below 30-40 nm (Fig. 4). Current technologies with bulk materials and conventional MgO-based MTJs will reach their limit in various fronts, including PMA and tunnel-barrier roughness. Within this context, the development of 2DM-based spintronic devices has been spectacular, providing opportunities for technological progress. In particular, magnetization switching by SOT has been recently observed in stacks incorporating 2DMs 135 whereas practical VCMA could become a reality by taking advantage of their ultrathin, atomically smooth properties. Large-scale integration of 2DMs in a fab environment will be accelerated in the coming years by efforts such as the 2D Experimental Pilot Line (Fig. 4), which will be the first foundry to integrate graphene and layered materials into semiconductor platforms 198 . Therefore, it is natural to envision that the large family of 2DMs could frame the roadmap for future advances of non-volatile spin-torque memory technologies. Many technical material and technical challenges remain. However, given the unprecedented speed at which progress is achieved and the high pace at which new 2DMs are discovered and characterized, we should be optimistic for the forthcoming steps towards moving to higher technology-readiness levels. This could not only potentially frame further commercial exploitation of 2DM-based non-volatile memory technologies but also serve as pathfinders for the exploration of spin-based logics and functionalized other spintronics devices 4,199 .