This is the accepted version of the journal article:
Yang, Hyunsoo; Valenzuela, Sergio O.; Chshiev, Mairbek; [et al.]. «Two-
dimensional materials prospects for non-volatile spintronic memories». Nature,
Vol. 606, issue 7915 (June 2022), p. 663-673. DOI 10.1038/s41586-022-04768-0
This version is available at https://ddd.uab.cat/record/269764
under the terms of the license
Two-dimensional Materials Prospects for Non-volatile Spintronic Memories
Hyunsoo Yang1,*, Sergio O. Valenzuela 2,3,* Mairbek Chshiev4,5, Sébastien Couet6, Bernard Dieny4,
Bruno Dlubak7, Albert Fert7, Kevin Garello4,6, Matthieu Jamet4, Dae-Eun Jeong8, Kangho Lee9,
Taeyoung Lee10, Marie-Blandine Martin7,11, Gouri Sankar Kar6, Pierre Sénéor7, Hyeon-Jin Shin12 and
Stephan Roche2,3,*
1
Department of Electrical and Computer Engineering, National University of Singapore, 117576
Singapore
2
Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and BIST, Campus UAB,
Bellaterra, 08193 Barcelona, Spain
3
ICREA, Institució Catalana de Recerca i Estudis Avancats, 08010 Barcelona, Spain
4
Univ. Grenoble Alpes, CEA, CNRS, SPINTEC, 38000, Grenoble, France
5
Institut Universitaire de France (IUF), 75231, Paris, France
6
IMEC, Kapeldreef 75, 3001 Heverlee, Belgium
7
Unité Mixte de Physique, CNRS, Thales, Université Paris-Saclay, 91767 Palaiseau, France
8
R&D Center, Samsung Electronics Co., Hwasung, South Korea
9
Foundry Business, Samsung Electronics Co., Giheung, South Korea
10
GLOBALFOUNDRIES Singapore Pte. Ltd., 738406 Singapore
11
Thales Research and Technology, 91767 Palaiseau, France
Inorganic Material Lab., Samsung Advanced Institute of Technology (SAIT), 16678, South Korea
12
*corresponding authors
Non-volatile magnetic random access memories such as spin-transfer torque (STT)-
MRAM and next generation spin-orbit torque (SOT)-MRAM are emerging as key
enabling low-power technologies, which are expected to spread over large markets from
embedded memories to the Internet of Things. Concurrently, the development and
performances of devices based on two-dimensional (2D) van der Waals heterostructures
bring ultra-compact multilayer compounds with unprecedented material-engineering
capabilities. Here, we first provide an overview of the current developments and
challenges in the field, and then outline the opportunities which can arise by
implementing 2D materials into spin-based memory technologies. We highlight the
fundamental properties of atomically smooth interfaces, the reduced material
intermixing, the crystal symmetries and the proximity effects as the key drivers for
possible disruptive improvements for MRAM at advanced technology nodes.
1
Emerging technologies generally follow a hype cycle before reaching the mature production
stage. When NAND Flash memory was first commercialized in 1989, it competed against
conventional non-volatile memories such as electrically erasable programmable read-only
memory (EEPROM)1. Even when its market size reached over $1.8B in 1995, the
semiconductor industry was still uncertain about the full potential of this technology. However,
new applications such as MP3 players and smart phones, which rapidly increased end-use
demands, fuelled NAND Flash development to reduce cost per bit, resulting nowadays in 3D
NAND Flash innovation2. Mobility and miniaturization trends in consumer electronics have
continuously driven the NAND Flash market, which reached over $50B in 2020.3 On the other
hand, while their potential in terms of low power and speed is proven, spintronic memories are
still emerging in terms of market size. The most advanced emerging generation of MRAM,
based on spin-transfer torque mechanism (Fig. 1), is already addressing a few market segments.
However, it is envisioned that, in the near future, the MRAM market will expand significantly
by addressing the power and data-transfer (memory-wall bottleneck) challenges in a variety of
embedded applications, including neural networks and in-memory computing4,5. Considering
that the embedded emerging non-volatile memory market is forecasted to grow from $20M in
2019 to $2.5B by 2025,6 it could well drive MRAM growth, as mobile consumer electronics
has driven NAND Flash in the past. In order to achieve such a growth, MRAM technology will
meet a variety of challenges requiring material and device integration breakthroughs, in which
two-dimensional materials (2DMs) could play a key role.
Indeed, since the discovery of graphene, followed by an ever-growing family of related
materials7, 2DMs have emerged as potential enablers for potentially ultra-compact device
architectures or radically new concepts for spin information processing8,9. Scientific advances
of 2DM-based spintronic devices as well as recent progress in large-scale co-integration of
2
2DMs with conventional microelectronics materials10,11, open a promising perspective for
developing innovative MRAM technology.
Here, we provide an overview of the most recent developments, identify challenges
and opportunities brought by 2DMs for MRAM and give a vision about how progress in 2DMs
research could morph into a game changing solution for future generations of spintronic
memory technologies. We first describe fundamental MRAM concepts and the prospects for
MRAM commercialisation, including the main roadblocks for broader deployment. We then
highlight the unique opportunities brought by 2DMs and van der Waals (vdW) heterostructures
to overcome some of the technological challenges. Afterwards, we analyse the requirements
and challenges for further advances concerning growth, processing, and integration of 2DMs
to enable an impact in next generation spintronic-memory development. Finally, an outlook
provides a vision of 2DM-MRAM technologies.
STT-MRAM and next generation SOT-MRAM
Non-volatile MRAM technologies are built on magnetic tunnel junctions (MTJ) comprised of
two ferromagnetic (FM) layers separated by a thin insulator. One of the FM layers, known as
the free layer (FL), stores information, while the other, the reference layer (RL), provides a
stable reference for reading the FL information. Two main technologies relying on electrically
generated spin-currents have emerged to control the FL magnetization: spin transfer torque
(STT)12 and spin orbit torque (SOT)13.
The STT concept was first introduced in 199614,15 and implemented at STT-MRAM
chip level in 200516. STT is observed in a two-terminal geometry, in which a vertical current
is injected through the MTJ (Fig. 1a). The current tunnelling through the barrier is spin-
polarized, leading to the FL magnetization reversal for large enough currents, due to the
transfer of angular momentum. The relative magnetization orientation of the FL and RL layers
3
determines the resistance of the device, which is monitored by the tunnelling magnetoresistance
(TMR).
SOT-MRAM is based on three-terminal devices, where an additional conducting path
is added adjacent to the FL (Fig. 1b). A charge current flowing through this path results in the
injection of a spin-polarized current into the FL in virtue of the spin-Hall and/or Rashba-
Edelstein effect13,17-19. In such devices, SOT can switch the FL magnetization without passing
a current through the MTJ tunnel barrier. At the expense of adding another terminal, the
decoupling of the write and read current paths prevents write errors during read operation and
reduces the risk of voltage breakdown. It further enables versatile cell designs by allowing the
spin torque direction to be set independently of the anisotropy direction in the stack20. Using
SOT, magnetization switching has been observed in the ps time scale21.
Commercialization and challenges of spin memory
Successful commercialization of STT-MRAM in solid-state drives (SSD) and wearable
electronics (Box 1) has been achieved after several major breakthroughs in MTJ technologies22,
including enhanced STT-switching efficiency and TMR amplitude, interfacial perpendicular
magnetic anisotropy (PMA) at magnetic metal/oxide interfaces23-25, synthetic antiferromagnets
(SAF), the suppression of etch-induced sidewall re-deposition and reduction in process
variability (Fig. 2). To cover a broader range of envisioned applications (Box 1), further
development of cost-effective and versatile MRAM technology will be crucial. It will also be
necessary to ensure proper downscaling to maintain competitiveness at advanced technology
nodes, in particular regarding MTJ diameter and cell-to-cell pitch. For example, because of the
required analog circuitry, as a rule of thumb it is desirable to keep the STT-MRAM bitcell
about 3 times smaller than the SRAM cell size at a given technology node so that the benefit
is worth the technology change.
4
Improving the MTJ stacks and their versatility using conventional materials and
integration processes is a difficult challenge. The actual stacks consist of dozens of ultra-thin
layers (Fig. 1) in which each material and interface plays an important role in determining the
device performance (Fig. 2). Below, we discuss some of these important aspects. In terms of
materials, modern MRAMs rely on the crystalline MgO tunnel barrier, while the FM layers
that are in contact with MgO are typically made of crystalline CoFeB (Fig. 2a). The
CoFeB/MgO/CoFeB combination is attractive because of its high TMR ratio originating from
the spin filtering effect in crystalline-MgO/FM, as predicted in 200126 (Fig. 2b). The structure
appears to be simple but practical devices are far more complex. The RL layer requires a much
higher magnetic anisotropy than the FL to be stable during memory operation. For this purpose,
almost all MRAMs use a multilayer SAF to pin the RL (Fig. 2c), which relies on strong
antiferromagnetic coupling between two ferromagnetic layers, and gives rise to a magnetically
hard structure.
Another crucial point is PMA23-25 (Fig. 2d) because perpendicularly magnetized stacks
have a better scalability than the in-plane magnetized counterparts. Due to the switching
dynamics induced by STT, a better trade-off between the thermal stability of the FL
magnetization and the write current is obtained in out-of-plane magnetized MTJs27. Interfacial
PMA can originate from spin-orbit interactions deriving from electronic hybridization effects,
magnetocrystalline anisotropy, and interfacial strain. PMA was demonstrated in a
Ta/CoFeB/MgO structure24 but requires very thin CoFeB, which results in increased damping
from the spin pumping effect and less efficient STT, while the anisotropy strength is
insufficient for small devices (< 30 nm). A solution for these issues involves double MgO
barriers, such as MgO/CoFeB/MgO and MgO/CoFeB/Ta/CoFeB/MgO (Fig. 2d). Here, having
the FL between two oxide barriers effectively increases the anisotropy28,29, providing thermal
stability of the magnetization down to ~20-nm cell diameter30. Other approaches to enhance
5
PMA below 20 nm rely on vertical shape anisotropy31,32, but these concepts face manufacturing
challenges due to the large MTJ aspect ratio.
As the MTJ size is downscaled, the TMR must remain high enough while an increase
in the PMA is required to maintain thermal stability and data retention. However, the enhanced
anisotropy of these structures forces the use of large current densities to achieve reliable
magnetization switching, which increases energy consumption. As such, introducing voltage
controlled magnetic anisotropy (VCMA) to assist or induce the switching could be helpful (Fig.
2e). It has been shown that a voltage across the MgO tunnel barrier results in charge
accumulation near the FL/MgO interface, inducing atomic-orbitals occupancy changes that
modulate the magnetic anisotropy33-35. VCMA-assisted writing could therefore reduce the
energy dissipation and memory cell area by lowering the driving current. Unfortunately, the
strength of the VCMA effect in CoFeB/MgO remains insufficient for practical
implementations.
Pitch scaling also tends to increase the failure rate by forming shunting paths on the
sidewall due to metallic re-deposition during MTJ patterning.36 The physical and chemical
damages on the pillar sidewall become even more problematic for downscaled MTJ devices.
Broken symmetry of atomic bonding on the sidewall from physical bombardment or chemical
diffusion of etching gases significantly degrades both the spin polarization and the magnetic
anisotropy. Finally, another important issue is related to atomic intermixing at interfaces, taking
place between the metallic layers in the MTJ during the post thermal annealing at ~400 °C
required to improve the MTJ crystallinity and CMOS integration (Fig. 2f). When intermixing
reaches the tunnel barrier, it leads to performance deterioration. This issue becomes more
relevant as the thickness of the layers is reduced at advanced nodes, since the risk of failure of
the tunnel barrier increases when the layer roughness becomes comparable to its thickness.
6
There are also various integration and material challenges associated to SOT-MRAM
(Fig. 2g). SOT-MRAM uses the technological platform of STT-MRAM, thus knowledge and
solutions developed for STT-MRAM could be transferable to SOT-MRAM development.
However, a fundamental difference lies in the stack design. While in STT-MRAM the FL
generally is on the top of the MTJ stack (bottom pinned, Fig. 1c) in SOT-MRAM, it is on the
bottom (top pinned, Fig. 1d). This forces to re-design material growth protocols and to
introduce specific seed layers to achieve the desired crystallinity of MTJs. Stacks with in-plane
magnetization increase the SOT cell size, although they have the benefit of magnetic field-free
switching. In contrast, for deterministic switching of perpendicular anisotropy SOT devices,
an in-plane external magnetic field along the current direction is required (Fig. 2g). This
magnetic field is a major hurdle for practical SOT-MRAM applications. Various solutions have
been proposed to obtain field-free switching such as complex shapes37,38, the use of in-plane
MTJ39 that limits scalability and speed, the insertion of an in-plane magnet below the SOT line
increasing writing currents40, or using antiferromagnetic heavy metal SOT lines41. Although a
solution embedding a magnet in 12-inch wafer integration process was demonstrated42, this
solution comes at the expense of uniformity, cost, security, and MTJ stability.
Opportunities with 2DMs for MRAM
Major progress in spin-torque memory technologies have been achieved by material
developments. However, to date, only a very limited number of optimal material combinations
have been identified, in particular CoFeB/MgO has played a prominent role for nearly two
decades since no alternative has been found yet. Consequently, MRAM technology faces
severe constraints, threatening its future evolution and broad deployment. In recent years, wide
varieties of novel emerging 2DMs and heterostructures have shown the potential to address the
aforementioned issues and challenges. In a monolayer form, 2DMs are atomically thin and
their interfaces are atomically smooth. They interact weakly, through vdW interaction, with
7
minimal element intermixing. In addition, given their atomically-thin nature, their properties
could be tuned by external electric fields or proximity effects9. They exist in metallic, insulating,
semiconducting, ferromagnetic and antiferromagnetic forms without or with broken crystalline
symmetries, and presumably, they can be stacked in any preferred combination and order.
Therefore, the properties and versatility of 2DMs make them very attractive for
spintronics and, in particular, for memory technologies, which strongly rely on ultrathin
materials and their interfaces to harness the required functionalities (Fig. 2). Although 2DMs-
based technologies are far from reaching the level of maturity of MgO/CoFeB based MTJs (for
example the first 2D magnets were isolated in a monolayer form just a few years ago and are
right now barely exceeding room temperature operation)43-46 vdW heterostructures are taking
an increasingly prominent role in spintronics research.
Interfacial PMA and synthetic antiferromagnets
As the MTJ size scales down, the energy barrier to switch the FL decreases, which in turn
increases its bit-to-bit variation, hence degrading data retention47. In principle, intrinsic
interfacial PMA (Fig. 2d) can be enhanced by using FM materials with large spin-orbit
coupling23. However, the use of an amorphous FM alloy is preferred to achieve epitaxial
crystallization of the MgO barrier upon annealing,48 which constrains the selection of the FM
material. Besides, increasing the spin-orbit coupling in the FL would increase the damping and
the write current23. Accordingly, there is a crucial need for innovative material alternatives to
enable STT-MRAM below 15-20 nm.
In this context, 2DMs have been investigated as promoters of large PMA. The
combination of graphene with Co, Fe, and/or FePd has shown promising results49-53. For
example, calculations show that the PMA of Co films coated by graphene (on one or both
surfaces) is enhanced by up to 100% compared to the PMA of pure cobalt, reaching an upper
value of ~2 mJ/m2.51 The critical thickness of Co at which the out-of-plane to in-plane
8
magnetization transition occurs (>13 ML or >2.6 nm) increases, as confirmed experimentally
with graphene/Co/Ir(111) samples50,51 (Fig. 2d). In comparison, the PMA of pure Co vanishes
beyond 7 ML. Downscaling potential to a MTJ pillar diameter of 10 nm has been estimated
when both Co surfaces are covered by graphene or for FePd/Graphene interfaces54 (Fig. 2d).
Interestingly, graphene also presents potential for implementing SAFs, as revealed by the
strong antiferromagnetic exchange coupling across a graphene spacer in out-of-plane
magnetized FM/graphene/FM structures (Fig. 2c)51,52,55. The integration of graphene-based FL
in STT/SOT-MRAM could minimize the Dzyaloshinskii–Moriya interaction arising at
Co/graphene interfaces56, which has a detrimental effect on device switching performance57-60.
Encapsulation and intermixing suppression
As the lateral dimension of MTJs shrinks, device morphology profiles become very rough and
non-uniform. Chemical vapour based 2DMs embedded in the MTJs can help overcome
fabrication challenges and improve the device morphology as the tunnel barrier thickness and
lateral dimension downscale (Fig. 2). Their atomically thin, flexible and generally inert nature
can minimize defects related to dangling bonds, interface states and interfacial alloy
formation61. For example, graphene can be simultaneously used as a contact and heat
dissipation layer and hBN as an encapsulation and insulating layer.
2DMs can suppress diffusion of atoms in MTJs. Intermixing reaching the tunnel barrier
eventually leads to device performance deterioration. Graphene and hBN have a dense electron
cloud structure and a low chemical reactivity due to their compact hexagonal honeycomb-
lattice, making it difficult for even the smallest He atom to spread. For this reason, 2DMs have
been heralded as atomically thin impermeable membranes62,63 to prevent the oxidation and
corrosion of metals64,65 and allow novel processes for spintronics such as atomic layer
deposition (ALD)66,67. Large area 2DMs uniformly grown by CVD can therefore be used as an
encapsulating layer to protect patterned MTJ cells from the post thermal and inter-diffusion of
9
BEOL processes (Fig. 2f). Similarly, many organic materials (as used in OLED for instance)
hold tailoring potential for spintronics68, which 2DMs integration could unleash by stabilizing
interfaces.
Thickness engineering of material spacers follow a trade-off relationship.25,69,70 A thick
spacer could provide suitable texture decoupling and diffusion barrier, but the magnetic
coupling weakens. 2DMs could provide ideal spacers since the trade-off relationship can be
efficiently optimized. Large-scale 2DMs grown by CVD on FMs71-73 preserve interfaces with
spin polarized metallic states even after exposure to oxidative conditions.66,67,74,75 Graphene
and hBN have demonstrated outstanding performance as atomic diffusion barriers down to the
monolayer.67,76,77 Notably, large-scale graphene growth on high magneto-crystalline anisotropy
and low magnetic damping FePd L10 PMA ordered alloy was recently achieved53.
Additionally, the oxidation issue of FMs usually forbids low-cost ambient/oxidative
processes such as ALD, which are widely used in the microelectronics industry.78,79 ALD based
Al2O3 and MgO tunnel barrier integration in spin valves have been demonstrated66,80,81,
showing high quality coverage with conformal and layer-by-layer growth at the angstrom limit
(Fig. 2f). This hints the potential of 2DMs to unlock processes (ALD, use of organics) with
implications to oxidation-resistant and enabled low-cost approaches.
Alternative tunnel barriers
2DMs cover a wide range of electronic properties from metallic (TiS2) and semimetallic
(graphene, WTe2, MoTe2) to semiconducting (MoS2, MoSe2, WS2, WSe2, black phosphorous,
etc) and insulating (hBN) and can also exhibit topological properties (Bi2Se3, Bi2Te3, WTe2,
MoTe2).82-84 2D magnets such as CrI3, CrTe2, Cr2Ge2Te6 and Fe3GeTe2 have been recently
added to this family43,85-88, offering great potential for the replacement of bulk FMs and,
perhaps, TMR enhancement.
The demand for controlling the thickness of oxide tunnel barriers with atomic level
10
precision represents a serious challenge. The spintronics community is struggling to achieve
and control ultra-thin MgO tunnel barriers with homogeneous thickness over a large scale.89,90
The natural aptitude of 2DM tunnel barriers, which can be defined layer by layer with atomic
precision, is one of the key advantages (Figs. 2b and 2f).91-96 Nonmagnetic materials, such as
graphene, hBN and transition metal dichalcogenides (TMDC) MoS2 and WS2, have been
demonstrated as a tunnel barrier in MTJs, exhibiting novel band structures or hybridization
spin filtering effects and leading to a sizeable TMR value up to 80% with predictions as high
as 1012%.76,77,80,91,97-107 Experimental demonstration of the direct integration of graphene in
TMR devices has been carried out in CMOS compatible processes (< 450 °C with large-scale
CVD)67. Owing to the development of large-scale technologies, such as CVD, molecular beam
epitaxy (MBE) and pulse laser deposition (PLD), other 2DMs have been investigated for
MTJs76,101,108-114.
It is important to note that theoretical ab-initio studies on CoFe/MgO/CoFe based MTJ
have predicted TMRs26 in the range of several 1000% whereas experimentally the room-
temperature record is 604%, while the TMR in commercial products is ~200%.115,116 This
discrepancy is due to defects in the MgO tunnel barrier, lattice mismatch between MgO and
FM, diffusion of boron or other elements towards the MgO barrier, etc. With 2DMs, the MTJ
stack could be closer to the ideal one thanks to their high stability, suppressed diffusion, and
well-defined interfaces, which would favour downscaling. For example, all-2D based MTJs
comprising a 2D tunnel barrier and 2D magnetic layers could be envisioned (Fig. 2f). A TMR
of 160% at low temperature has been reported in a MTJ entirely made of 2DMs
(Fe3GeTe2/hBN/Fe3GeTe2), with PMA and a spin polarization exceeding 60% gate tunability99.
Even a larger TMR was predicted in Fe3GeTe2-based MTJs for various vdW spacers117.
Furthermore, the fact that 2DMs and their heterostructures are atomically thin
promises less technological efforts to process them into functional devices, avoiding
11
technological steps such as planarization. They could further enable novel memory elements
as alternatives to traditional MTJs (Fig. 2b). A low-temperature magnetoresistance as large as
19000% was observed in tunnel junctions of four-layer CrI3, a layered insulating
antiferromagnet118,119, while a TMR up to 100000% was predicted for VSe2120.
Spin-orbit torques
Compared to SRAM, the stand-by power of SOT-MRAM is negligible, but projected write (<
75 fJ) and read energies (< 25 fJ) using state-of-art stacks must be reduced121. Reading is
directly linked to the minimum current detectable by the sense amplifiers and stand-by power.
For fast reading < 5 ns with ~150−200% TMR, the read current should be ~50−80 µA. Typical
transistor current capabilities in sub-28 nm technology nodes with minimum footprint is on the
order of 30-100 µA, while state-of-the-art perpendicular SOT-MRAM projects a critical write
current of ~300 µA per bit cell121,122. Hence, to prevent CMOS from dominating the cell size,
a straightforward way is to improve the SOT efficiency ξ, the conversion ratio between spin
and charge currents, to ξ > 1, while heavy metal layers, such as Pt and W, yield ξ = 0.1-0.5 122-
124
.
The integration of 2DMs provides appealing opportunities for SOT-MRAM. The large
spin-orbit coupling and associated spin textures of 2DMs, including TMDCs and topological
insulators (TIs), make them serious candidates for inducing large spin torques. The most
studied TIs are the Bi2Se3 and (Bi1-xSbx)2Te3 family of materials. The observation of large
damping-like torques and the achievement of room-temperature magnetization switching
confirms their potential for SOT-MRAM.125,126 Because of the reduced crystal symmetry of
some TMDCs, unconventional torque components are also expected. Of significant relevance,
an out-of-plane damping-like torque can be induced by WTe2 and NbSe2127,128 (Fig. 2g), which
could enable field-free SOT switching in perpendicular SOT-MRAM. A pronounced SOT is
expected not only from the bulk but also from the surface in topological Weyl semimetals.
12
Room-temperature magnetization switching in a regime of domain wall motion has been
reported in WTe2/Py and WTex/Mo/CoFeB heterostructures127,129,130.
Magnetization switching by SOT was also achieved in hybrid 2D/3D systems. Such is
the case of Fe3GeTe2 or Cr2Ge2Te6 at low temperature using an adjacent heavy-metal layer131-
134
. Large SOTs have also been reported in Py/WS2 and CoFeB/(MoS2 or WSe2) bilayers135,136.
A modulation of the coercivity with currents has been reported in Fe3GeTe2/WTe2137, and SOT
switching was observed up to the Curie temperature (~200 K) of Fe3GeTe2 in WTe2 (12.6
nm)/Fe3GeTe2 (7.3 nm) with PMA138.
Engineering and tuning material properties
The control of the magnetic anisotropy with electric fields (VCMA) provides an engineering
knob to optimize the trade-off between data retention and writability as well as to reduce the
energy consumption. In current MTJs using metalling FMs, electric fields only penetrate a few
Angstroms into the film surface, limiting the efficiency to control the magnetic properties. In
contrast, the 2D magnets magnetic properties, Curie temperature and magnetic anisotropy, and
spin filtering thru MgO are largely tunable using external stimuli such as electric fields87,
strain139-142 or light.
Another exciting aspect is to leverage on the asset of hybridization (proximity or
interface effect)9,68,92,143 that could allow spin filtering and resistance-area product reduction (<
Ω⋅µm2). In proximity with a FM, the large gap insulating hBN have already shown to become
metallic leading to spin filtering and a TMR of 50% in an 2D-MTJ76 . Similarly, for graphene
it was also possible to reach a TMR of 80%.77 Other 2DMs such as TMDCs (with specific
thickness dependent band structure mechanisms) are now explored to further tailor spin
selection at FM interfaces101. Finally, graphene can further increase the current at the boundary
between large spin-orbit coupling material and the FM. Room-temperature, proximity-induced
spin orbit coupling effects, which are tunable by gating, have been recently observed in
13
graphene/WS2144. In combination with the proximity-induced effect, an enhanced spin torque
could be obtained.
Material and integration challenges
Material challenges
MRAM is expected to progressively become mainstream in rapidly expanding areas such as
IoT and Artificial Intelligence-based devices (Box 1) for which the development of cost-
effective, downscaled MRAM technology will be essential145. However, the limited portfolio
of the available state-of-the-art 3D materials and architectures could become an
unsurmountable obstacle for the industry. In this regard, 2DMs offer unique opportunities; to
advance their use, several notable challenges lie ahead that require material research and
development, in hand with engineering efforts146,147.
There are thousands of predicted stable 2DMs, including insulators, semimetals,
magnets and novel electronic phases, such as Weyl semimetals or topological insulators148-150.
Many of them have properties that make them potentially attractive for magnetic memory
technologies. Substantial attention must therefore be directed towards identifying and
characterizing the most promising candidates to optimize MRAM performance. MTJs
incorporating 2DM tunnel barriers92 currently present TMR values77 that are already
comparable to those of the first generation of crystalline MgO barriers151 that later became
technologically relevant devices115,116. This is reinforced by the added potential of the newly
developed 2D magnets. While we cannot predict whether such a suitable 2DM for memories
will be available anytime soon, we can highlight tremendous efforts by the community in this
direction43-46. Indeed, considering that the first 2D magnets were reported in 201785,86 already
observing 2D magnets with a Curie temperatures near room temperature is impressive and
efforts are undergoing to achieve this objective, relying on new material sets, improved control
and sample quality, and doping approaches.152-157 Hence, despite the results being not yet
14
competitive for nowadays room temperature standards, the tremendous effort made by the
community and the fast pace of progress made in the recent years (from tunnel barriers to 2D
magnets) to target functional large-scale spin-based technologies allow to envision the
possibility of functional large-scale spin-based technologies operating at room temperature in
the not so distant future.
Reported SOT efficiencies with 2DMs, especially TIs, largely surpass those of heavy
metals. Crystal-dependent symmetries for field-free switching and VCMA are phenomena not
easily implemented in today’s MRAM materials. However, most SOT studies use micron-scale
devices, where magnetization switching may occur via mechanisms with low activation
barriers, such as domain motion. Future research efforts are required to extend these studies to
practical sub-100-nm devices. In hybrid systems, the reactivity between 3D transition metals
and 2D chalcogenides changes the nature of the interface, which may form uncontrolled
interfaces due to chemical reaction158-161. Alloys and magnetic dead layers can modify the
underlying SOT mechanisms160,161. However, if mastered, hybridization could become an asset
for moving toward ultra-compact geometries68,160. All-2D vdW heterostructure would provide
an opportunity to control SOT phenomena and may help overcome diffusion issues.
Explorative experiments with 2DMs are typically carried out using micrometre-sized
flakes exfoliated mechanically from bulk materials. This technique is not up-scalable. The
development of 12-inch wafer-scale CMOS-compatible growth process (direct growth on
process wafer or layer transfer, Fig. 3a) is thus necessary to address the scalability issue; this
remains a critical challenge for any 2DM implementation in microelectronics146,147.
Furthermore, follow-up integration processes will need to maintain the original structure and
device performance of 2DMs (delamination risk elimination, surface treatments, low damage
co-integration with MRAM stacks, Figs. 3b and 3c).
Large scale growth
15
Growth methods to obtain uniform 2D layers on large areas could be based either on chemical
methods (e.g. CVD) or on physical deposition such as MBE, PLD, and sputtering113,114,146,162-
169
(Fig. 3a). Chemical routes are arguably the most promising thanks to their low cost and
compatibility with large wafer processing but progress so far is limited to a few selected
materials. Single-crystal graphene and hBN growth has been scaled beyond 6-inch wafer at
over 1000 °C using CVD170-172 although single-crystal growth remains to be achieved,
polycrystalline graphene growth has been demonstrated at 450 °C with plasma CVD173,174.
During CVD growth, precursors react in the vapour phase in the wafer surface (650 −1000 °C).
A low nucleation rate leads to the formation of large isolated flakes of high crystalline quality,
which cover only a very small fraction of the substrate, with randomly oriented domains and
poor control of the number of layers. The use of less stable metal and chalcogen precursors in
TMDCs growth reduces the growth temperature (300−560 °C) and increase the nucleation
rate175-177. Precursor control growth could drastically reduce the thermal budget for the
fabrication, which is a promising approach for direct growth in BEOL compatible wafers.
Using this technique, monolayers of TMDCs are grown over a wafer scale, but they remain
polycrystalline, which degrades their electrical properties.
Processing and integration
After the growth over large areas of high crystalline quality 2DMs, their transfer from
the growth to the target substrate is required for further processing and device integration (Fig.
3b). In this respect, the technological challenge consists of maintaining the 2D layer integrity
during the process. The most widely used approach is the polymer-assisted transfer, in which
a polymer film is used to mechanically support the 2DM178-180. The release from the growth
substrate could be achieved in a solution by electrochemistry, chemical dissolution of the
substrate or simply intercalation of water between the substrate and 2DM. Recently, another
transfer method called spalling has been developed where the 2DM is detached from the
16
substrate by the strain induced by a metallic film grown onto it181,182. The metal/2DM stack is
then transferred onto the target substrate and the metallic film is chemically etched.
Although 2DMs are generally compatible with standard integration processes such as
photolithography, etch, and deposition, significant process optimization would still be needed
to maintain the original structure and properties of the 2DMs. Of particular relevance are
reducing damage in plasma-based processes, increasing adhesion and suppressing material
lifting in chemical processes, and patterning by etching in combination with selective stop
techniques183-187. Another point of attention is to retain the original structure of 2DMs without
self-deformation, degradation and interference with other layers. For instance, the deposition
of a conventional MRAM stack is carried out using sputtering, which can expose the 2DM seed
to a plasma that can easily damage the 2DM. Some solutions have been proved viable (off-axis,
flipped chip)188 and have to be adapted to large scale tools, such that the deposition condition
can be modified to be damage-free (see Fig. 3c as an example) while not degrading magnetic
properties and stack performances.
Outlook and roadmap
Today, a variety of memory technologies complement each other for computing, data storage,
and embedded applications. Figure 4 outlines a roadmap for MRAM. STT-MRAM has been
already commercialized for persistent memory in storage devices and servers as well as
wearable electronics. MRAM is fostering key emerging markets, such as wearable, automobile,
IoT, biosensor, various cache, and buffer memory applications. Its development over recent
years has been astonishing and it is clear that it will shortly play a central role in the embedded
non-volatile memory market.
However, the requirements of each application vary significantly as summarized in
Table 1. Flash-replacement STT-MRAM requires high data retention (> 20 years) but accepts
low endurance (106 cycles). In contrast, SRAM-replacement STT-MRAM requires high
17
endurance (> 1012 cycles) and high bandwidth but needs much less data retention, even down
to a few seconds. One major challenge for automotive applications is reliable chip operation
even under extreme environment such as a high temperature of 150 °C or exposure to external
magnetic fields that can increase the bit error rate. Good read margin up to 150 °C and magnetic
immunity to guarantee 10 years reliability were demonstrated47,189,190. Finally, both bit-cell size
reduction and operation speed enhancement are key factors in order to expand into the SRAM-
replacement area. Recently, a write/read speed less than 10 ns and 1012 cycling endurance was
demonstrated191 showing a promise for SRAM replacement. On the other hand, SOT-MRAM
is still a topic of intense research and under industrial initial assessment122-124. In order to move
forward, the first step is to establish the manufacturability using industrial CMOS compatible
processes. In fact, SOT-MRAM was recently demonstrated up to 12-inch scales42,122 with
reliable sub-ns switching, low error rates and high endurance on Ta/CoFeB/MgO or
W/CoFeB/MgO stacks using either perpendicular42,192-194 or in-plane39,195 magnetization.
It is however unknown how scaling beyond the 14-nm node will be achieved with
conventional materials, when the MTJ feature size is projected to be below 30-40 nm (Fig. 4).
Current technologies with bulk materials and conventional MgO–based MTJs will reach their
limit in various fronts, including PMA and tunnel barrier roughness. Within this context, the
development of 2DM-based spintronic devices has been spectacular, providing opportunities
for technological progress. In particular, magnetization switching by SOT has been recently
observed in stacks incorporating 2DMs134 while practical VCMA could become a reality by
taking advantage of their ultrathin, atomically smooth properties. Large-scale integration of
2DMs in a fab environment will be accelerated in the coming years by efforts such as the 2D
Experimental Pilot Line (Fig. 4), which will be the first foundry to integrate graphene and
layered materials into semiconductor platforms196. Therefore, it is natural to envision that the
large family of 2DMs could frame the roadmap for future advances of non-volatile spin-torque
18
memory technologies. Many technical material and technical challenges remain. However,
given the unprecedented speed at which progress is achieved and the high pace at which new
2DMs are discovered and characterized, we shall be optimistic for the forthcoming steps
towards moving to higher technology readiness levels. This could not only potentially frame
further commercial exploitation of 2DM-based non-volatile memory technologies, but also
serve as pathfinders for exploration of spin-based logics and functionalized other spintronics
devices4,197.
19
Table. 1. Specification comparison for various MRAM applications. Target applications
are indicated with brackets. Relevant 2DM technologies discussed in the main text are listed in
the last column.
20
Fig. 1 | State-of-the-art MRAM technologies. a and b, Schematics of STT-MRAM and SOT-MRAM cells with
perpendicular magnetic anisotropy (PMA), respectively. c, Bottom-pinned STT-MTJ sketch and transmission
electron microscopy (TEM) cross section of 45 nm diameter STT-MTJ consisting of a CoFeB free layer (FL),
MgO tunnel barrier and CoFeB/spacer/Co/Ru/[Co/Pt] reference layer (RL). The inset shows TEM cross section
of STT-MRAM array (top dash box) controlled by CMOS (bottom dash box). d, Top-pinned SOT-MTJ sketch
and TEM cross section of 60 nm SOT-MTJ. The inset shows a typical SOT-MRAM cell where the write current
is injected from bottom electrode BE1 to BE2, and the read current from top electrode (TE) to BE2. Images from
GlobalFoundries and IMEC.
21
Fig. 2 | Fundamental phenomena of MRAM cells and 2DM prospects. Current solutions are represented inside
the dashed circle. a, Typical STT-MRAM stack. FL and RL refer to the free and reference layer, respectively. The
yellow top and bottom rectangles represent cap and seed layers, respectively. b, Tunnelling magnetoresistance
(TMR). A change (∆R) in the resistance is observed when the magnetization of FL switches, indicated by a
switching from a blue to a red arrow. Modern MRAM technologies rely on coherent tunnelling across an MgO
crystalline barrier. Similar performances are predicted with 2DM barriers (left). Large magnetoresistance has been
observed in layered insulating antiferromagnets (right). c, Synthetic antiferromagnets (SAFs) are used to pin the
magnetization of the RL. Equivalent magnetic structures are observed in layered materials (top) or can be
artificially created (for example with Co/graphene, bottom). d, Interfacial perpendicular magnetic anisotropy
(PMA) is found at the interface of magnetic metals and oxides but also on graphene/FM heterostructures. e,
Voltage controlled magnetic anisotropy (VCMA) is observed at the interface of magnetic metals and oxides. Due
to their atomically thin nature, 2DMs enable enhanced tunability of their properties, including gating and
proximity effects. f, Intermixing and interface roughness becomes critical when scaling requires very thin (< 1
nm) tunnel barriers. This results in tunnel-barrier performance degradation and lack of reproducibility, which can
be circumvented with atomically smooth 2DMs and 2DM diffusion barriers. g, For perpendicularly magnetized
MTJs, an in-plane external magnetic field (H) along the current direction is typically required for switching. Low-
symmetry 2DMs could help to eliminate the need for such a magnetic field.
22
Fig. 3 | Challenges for integrating of 2DMs into MRAM technologies. a, Although significant progress has
been achieved in small-scale demonstration, 2DM technology faces challenges in large scale growth of the
materials for which several processes are being explored, from chemical, such as CVD, to physical such as
sputtering and MBE (WS2 on 300-mm glass carrier and target wafer is shown). b, Processing of 2D materials is
under development, in particular regarding transfer and patterning of multilayers. For large-scale production, the
development of suitable monitoring tools is also key. Graphene on a large wafer is shown. c, Integration in 2D-
MRAM technologies. TEM cross section of top-pinned MTJ stack deposited on large scale grown 2DM (here
WS2) [ref.198], showing no degradation of WS2. d, Potential implementation of 2DM in MRAM technologies as
seed, tunnel barrier, FMs, encapsulation and SOT layers.
23
Fig. 4 | Spin torque memory technology roadmap. The projected feature size of the magnetic tunnel junction
(MTJ) is shown at the top of the chart, together with the technology node at which a given MTJ size would be
introduced. STT-MRAM offers non-volatility together with low power consumption, which is ideal for low-power
microcontroller units (MCUs), wearables and IoT applications (Box 1). In terms of embedded non-volatile
memory (eNVM) technology, eFlash scaling will likely reach its end at the 28/22nm node. STT-MRAM is also
promising for automotive and SRAM replacement. Chipmakers and foundries started mass production for eFlash-
type STT-MRAM in 2018 and started to develop SRAM-type applications for cache. SOT-MRAM can address
high-speed and high-endurance applications such as cache and in-memory computing. The memory speed is best
characterized by the latency time, which includes electrical time delays induced by routing from selector control
to memory points and associated parasitic resistances and capacitances. As the memory size increases, the speed
tends to decrease. Current MRAM technologies based on bulk materials are expected to reach their limits at about
20-nm MTJ feature size, after which 2DMs could play a key role to maintain MRAM downscaling. Actual 2DM
milestones are shown at the bottom of the chart, including recent demonstrations of magnetization switching in
heterostructures comprising 2DM-SOT materials and/or 2D FMs. Enabling 2DM-based technologies are indicated
with STT and SOT technology projections and should be introduced at the indicated timelines to offset today’s
MRAM materials limitations. Efforts like the EU 2D Experimental Pilot Line are expected to accelerate the path
to production (see Ref196). HPC stands for high-performance computing.
24
Box 1
MRAM markets and commercialization
STT-MRAM is the only non-volatile memory capable of high-density, high-endurance and fast-write operation and
is considered as the best candidate for embedded non-volatile applications. The microcontroller units (MCU)
market in 2020 was over $25B and will be driven by 5G internet of things (IoT), wearable, general-purpose MCUs
and automotive electronics199. STT-MRAM can replace SRAM and NOR Flash in low-power MCUs, decreasing
cost and power consumption. STT-MRAM is also promising for memory replacement in the automotive and
biosensor sectors. There, embedded Flash (eFlash) is either not available or less cost-effective than embedded
MRAM beyond the 28-nm node. SOT-MRAM is under development and their applications would be primarily as
SRAM cache-memory replacement from L3/L4 to L2/L1 cache levels and registers in central (CPU) and graphical
processing units (GPU). SOT-MRAM has also potential in non-volatile logic elements200,201 and for in-memory
computing.202
STT-MRAM has been released down to 28 nm, where eFlash technology co-exists. However, eFlash scaling is
reaching its limits, while SRAM scaling becomes challenging due to stand-by leakage currents203. Applications
include enterprise SSD, storage-class memory and wearable electronics. In 2017, Everspin shipped standalone
256Mb STT-MRAM using GLOBALFOUNDRIES (GFs) 40-nm technology204 and started the production of 1Gb
STT-MRAM at the 28-nm node205. TSMC has also developed a 22-nm technology, while Samsung Foundry
commercialized in 2019 embedded STT-MRAM macro built upon low-power 28-nm fully depleted silicon-on-
insulator (FDSOI) platform206 (see Fig. 4). GFs has also delivered embedded STT-MRAM on its 22-nm FDSOI
platform for IoT and automotive applications207. Embedded STT-MRAM is expected to expand in low-power
wearable and RF applications, as demonstrated by Intel208.
Box Fig. 1 | Potential markets. MRAM is considered as the only non-volatile memory with high-density, endurance and fast
writing speed. Applications can be divided in three different categories: low-bandwidth (BW) non-volatile random access
memories (NVRAM), high-BW NVRAM, and NOR Flash replacement. The MRAM memory cell is formed at the back-end-
of-line (BEOL) without disturbing pre-established front-end processes (Fig. 1), which simplifies its implementation across
multiple technology nodes. SCM stands for storage class memory and AIoT for artificial intelligence of things.
25
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Acknowledgements
M.C., A.F., K.G., P.S., S.O.V. and S.R. acknowledge the European Union Horizon 2020
research and innovation program for grant number 881603 (Graphene Flagship). The Catalan
Institute of Nanoscience and Nanotechnology is supported by the Severo Ochoa Centres of
Excellence program, funded by the Spanish Research Agency (AEI, grant no. SEV-2017-0706).
S.O.V. thanks the European Research Council (ERC) under Grant Agreements 306652
SPINBOUND and 899896 SOTMEM and the Spanish Research Agency (AEI), Ministry of
Science and Innovation (PID2019-111773RB-I00/AEI/10.13039/501100011033). H.Y. is
supported by SpOT-LITE program (A*STAR grant, A18A6b0057) through RIE2020 funds,
Singapore Ministry of Education (MOE) Tier 1 (R263-000-D61-114), National Research
Foundation (NRF) Singapore Investigatorship (NRFI06-2020-0015) and Samsung Electronics’
University R&D program. S.C. and G.S.K. acknowledge IMEC’s Industrial Affiliation
Program on MRAM devices. M.C. and M.J. acknowledge the French National Research
Agency through the MAGICVALLEY project (ANR-18-CE24-0007). B.D. acknowledges
ERC MAGICAL 669204. M.C. acknowledges H.X. Yang, A. Hallal, F. Ibrahim. P.S. and B.D.
acknowledge the French National Research Agency through the SoGraphMem project (ANR-
18-CE24-0007).
Author contributions
All authors wrote and commented on the manuscript.
Competing interests The authors declare no competing interests.
Additional information
Reprints and permissions information is available at http://www.nature.com/reprints.
Correspondence and requests for materials should be addressed to H.Y.
(eleyang@nus.edu.sg), S.O.V. (SOV@icrea.cat) or S.R. (stephan.roche@icn2.cat).
38