d03f90b07efbb5c0946def9935e5e722 AppSci_a2023v13n12p7201.pdf b2fe49a47059a3edc6d63815ade71dfa74099cfc AppSci_a2023v13n12p7201.pdf 6b9a09e13edf5e8854c8d53120337e377738d359dc509284554adfb996aa5634 AppSci_a2023v13n12p7201.pdf Title: Investigating the Device Performance Variation of a Buried Locally Gated Al/Al2O3 Graphene Field-Effect Transistor Process Subject: In this study, a process is developed for the fabrication of buried top-gated graphene transistors with Al2O3 as a gate dielectric, yielding devices that can be suitable for not only flexible electronics but also laser-induced graphene (LIG)-based technology implementations. A new processing option is presented with the use of tetraethyl-orthosilicate (TEOS) as an etch stop for contact via etching of Al2O3. Buried locally gated Al/Al2O3 graphene field-effect transistors (GFETs) are fabricated with Dirac points as low as 4 V, with a metal-to-graphene contact resistance as low as 1.7 km, and an average hole mobility of 457.97 cm2/Vs with a non-uniformity of 93%. Large device variation and non-uniformity in electrical performance are not uncommon for graphene-based devices, as process-induced defects play a major role in such variation. AFM, SEM, Raman spectroscopy, and model fitting indicated that the rough Al/Al2O3 surface was the main factor for the observed device variation. AFM analysis indicated a graphene surface roughness Ra of 16.19 nm on top of the buried Al/Al2O3 gate in contrast to a Ra of 4.06 nm over Al2O3/SiO2. The results presented indicate the need to reduce device variability and non-uniformity by improving transfer methods, as well as the use of smoother surfaces and compatible materials. The presented analyses provide a framework with which other researchers can analyze and correlate device variation and non-uniformities while methods to reduce variability are investigated. Keywords: graphene; graphene field-effect transistors; 2D materials; gate dielectric; mobility; Dirac point; fabrication Author: Tzu-Jung Huang, Adheesh Ankolekar, Anibal Pacheco-Sanchez and Ivan Puchades Creator: LaTeX with hyperref Producer: pdfTeX-1.40.21 CreationDate: Fri Jun 16 08:42:36 2023 CEST ModDate: Tue Jun 27 03:47:00 2023 CEST Custom Metadata: no Metadata Stream: no Tagged: no UserProperties: no Suspects: no Form: none JavaScript: no Pages: 15 Encrypted: no Page size: 595.276 x 841.89 pts (A4) Page rot: 0 File size: 2732669 bytes Optimized: no PDF version: 1.7 name type encoding emb sub uni object ID ------------------------------------ ----------------- ---------------- --- --- --- --------- XHDYZV+VnURWPalladioL Type 1 Custom yes yes no 10 0 AYXMDM+EURM10 Type 1 Builtin yes yes no 15 0 ZNXRNU+URWPalladioL-Bold Type 1 Custom yes yes no 19 0 XLMJTV+URWPalladioL-Roma Type 1 Custom yes yes no 24 0 THNOQH+URWPalladioL-Ital Type 1 Custom yes yes no 28 0 EFDJON+CMSY10 Type 1 Builtin yes yes no 32 0 ROWTUD+PazoMath Type 1 Builtin yes yes no 36 0 CRVMKC+TimesNewRomanPS-BoldItalicMT Type 1C WinAnsi yes yes no 54 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 85 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 88 0 MOEPAF+PalatinoLinotype CID TrueType Identity-H yes yes yes 91 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 97 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 110 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 113 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 116 0 MOFAGA+PalatinoLinotype,BoldItalic TrueType WinAnsi yes yes no 119 0 JHYTSG+CMR10 Type 1 Builtin yes yes no 126 0 XQZHNR+PazoMath-Italic Type 1 Builtin yes yes no 130 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 137 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 140 0 MOEPAF+PalatinoLinotype CID TrueType Identity-H yes yes yes 143 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 149 0 MOFCND+CambriaMath TrueType WinAnsi yes yes no 159 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 162 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 165 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 168 0 MOFCNC+CambriaMath CID TrueType Identity-H yes yes yes 171 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 185 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 188 0 MOEPAF+PalatinoLinotype CID TrueType Identity-H yes yes yes 191 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 197 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 208 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 211 0 MOEPAF+PalatinoLinotype CID TrueType Identity-H yes yes yes 214 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 220 0 XIRVNA+EURB10 Type 1 Builtin yes yes no 227 0 TSEGZF+PazoMath-Bold Type 1 Builtin yes yes no 231 0 MOEOPD+PalatinoLinotype,Italic TrueType WinAnsi yes yes no 238 0 MOEOPF+PalatinoLinotype,Bold TrueType WinAnsi yes yes no 241 0 MOEPAF+PalatinoLinotype CID TrueType Identity-H yes yes yes 244 0 MOEPAG+PalatinoLinotype TrueType WinAnsi yes yes no 250 0 Jhove (Rel. 1.28.0, 2023-05-18) Date: 2024-03-14 02:36:48 CET RepresentationInformation: AppSci_a2023v13n12p7201.pdf ReportingModule: PDF-hul, Rel. 1.12.4 (2023-03-16) LastModified: 2024-03-13 14:33:10 CET Size: 2732669 Format: PDF Version: 1.7 Status: Well-Formed and valid SignatureMatches: PDF-hul MIMEtype: application/pdf PDFMetadata: Objects: 509 FreeObjects: 1 IncrementalUpdates: 0 DocumentCatalog: PageLayout: SinglePage PageMode: UseNone Outlines: Item: Title: Introduction Destination: section.1 Item: Title: Materials and Methods Destination: section.2 Children: Item: Title: Device Fabrication Destination: subsection.2.1 Item: Title: Graphene Transfer Destination: subsection.2.2 Item: Title: Test Methods Destination: subsection.2.3 Item: Title: Results and Discussion Destination: section.3 Item: Title: Conclusions Destination: section.4 Item: Title: References Destination: section.A. Info: Title: Investigating the Device Performance Variation of a Buried Locally Gated Al/Al2O3 Graphene Field-Effect Transistor Process Author: Tzu-Jung Huang, Adheesh Ankolekar, Anibal Pacheco-Sanchez and Ivan Puchades Subject: In this study, a process is developed for the fabrication of buried top-gated graphene transistors with Al2O3 as a gate dielectric, yielding devices that can be suitable for not only flexible electronics but also laser-induced graphene (LIG)-based technology implementations. A new processing option is presented with the use of tetraethyl-orthosilicate (TEOS) as an etch stop for contact via etching of Al2O3. Buried locally gated Al/Al2O3 graphene field-effect transistors (GFETs) are fabricated with Dirac points as low as 4 V, with a metal-to-graphene contact resistance as low as 1.7 km, and an average hole mobility of 457.97 cm2/Vs with a non-uniformity of 93%. Large device variation and non-uniformity in electrical performance are not uncommon for graphene-based devices, as process-induced defects play a major role in such variation. AFM, SEM, Raman spectroscopy, and model fitting indicated that the rough Al/Al2O3 surface was the main factor for the observed device variation. AFM analysis indicated a graphene surface roughness Ra of 16.19 nm on top of the buried Al/Al2O3 gate in contrast to a Ra of 4.06 nm over Al2O3/SiO2. The results presented indicate the need to reduce device variability and non-uniformity by improving transfer methods, as well as the use of smoother surfaces and compatible materials. The presented analyses provide a framework with which other researchers can analyze and correlate device variation and non-uniformities while methods to reduce variability are investigated. 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