This is the accepted version of the journal article: Valdivieso, Carlos; Rodríguez Martínez, Rosana; Crespo Yepes, Albert; [et al.]. «Resistive switching like-behavior in FD-SOI -gate transistors». Solid-state electronics, Vol. 209 (2023), p. 108759. DOI 10.1016/j.sse.2023.108759 This version is available at https://ddd.uab.cat/record/283391 under the terms of the license Resistive Switching like-behavior in quasi-planar FD-SOI transistors C. Valdivieso, R. Rodriguez, A. Crespo-Yepes, J. Martin-Martinez, M. Nafria Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) 08193, Bellaterra, Barcelona, Spain. email: carlosandres.valdivieso@uab.cat 1. Abstract In this work, the Resistive Switching (RS) phenomenon is experimentally investigated in N-type FDSOI quasi- planar NW-FETs with high-k dielectric. The location along the channel of the conductive filament through the device dielectric during switching is analyzed. Finally, the effects of RS on the characteristic transistor curves are also presented. 2. Introduction Resistive switching (RS) is a phenomenon that has gained importance in the last years because its potential exploitation in many applications such as non-volatile data storage, alternative computing architectures, cryptography, etc. [1]. RS can be observed in Metal-Insulator-Metal or Semiconductor (MIM/MIS) structures fabricated with specific materials [2]. In these devices, the dielectric resistance shows a non-linear current- voltage characteristic, and the dielectric conductance can be changed when subjected to a proper biasing. When bias is not applied, the device resistance presents a non-volatile behavior. RS phenomenon is usually attributed to the formation of a conductive filament through the device dielectric whose physical structure is directly related to the dielectric resistance [2]. In the case of MIS structures in MOSFETs, the analysis of the currents through the transistor terminals allows to obtain information about the location along the channel of the conductive filament in the gate dielectric [3]. Few works about RS in very scaled devices as Gate All Around (GAA) transistors are found in literature. In [4, 5] RS is observed in vertical GAA nanopillars integrated with RRAM cells, showing good non-volatile memory properties. In this work, the study of RS in FDSOI N-type quasi-planar NW-FETs is presented. The location of the conductive filament and the variation of transistor curves during switching are investigated. 3. Device Description and Measurement Procedure The FDSOI N-type quasi-planar NW-FETs under research were fabricated at CEA-LETI [6] and had a high-K dielectric stack (HfSiON/TiN) with EOT=1.3nm, HNW=11nm and a buried oxide (BOX) thickness of 145nm (Fig. 1). The devices were [110]-oriented. In this work, a single finger structure with gate width of W=10μm and gate length of L=10μm was used, which can be considered as quasi-planar SOI MOSFET [6]. The electrical measurements were performed with a Keithley 4200 Semiconductor Parameter Analyzer (SPA). To observe RS, firstly, a forming process was performed to create the conductive filament through the dielectric, by applying a voltage ramp from 0V to 4V with a 4mA current limit. The current limit is applied to avoid the irreversible hard breakdown of the dielectric. During RS, dielectric resistance changes between two different states, a Low Resistance State (LRS) and a High Resistance State (HRS). The transition from LRS to HRS is called reset process and the change between the HRS to LRS is named set process (Fig.2 left). The samples used in this work show bipolar RS, what means that positive/negative voltages are needed to provoke the set/reset processes respectively (Fig. 2 right). To perform the RS measurements, all four terminals of the transistor were contacted (Fig. 3). To provoke set processes, a positive ramp voltage from 0 to 5V with a compliance of 5mA was applied to the gate with the other three terminals grounded. The reset process was observed by applying a negative ramp voltage from 0 to -3.5V, with a compliance of 10mA, to the gate, with the other three terminals grounded. During the voltage sweeps (starting from 0 to 5V, continuing from 5V to -3.5V and finally from -3.5V to 0V) that produce the set and reset processes (RS cycle), the currents through the transistor terminals (IG, ID, IS, IB) were registered. 4. Results and Discussion Fig. 4 shows three consecutive experimental gate I-V curves in the same sample, after the forming process. Cycle-to-cycle dispersion of the set and reset voltages is observed. In the performed measurements, set/reset voltages vary between 2.5V to 5V and from -1.3V to -2.5V, respectively. Under this electrical conditions, 30 consecutive set/reset processes can be reached in these devices. The use of transistors allows the analysis of the RS filament location along the channel [3]. Fig. 5 shows the four terminals transistor currents as a function of VG measured simultaneously to the first (Fig. 5 left) and the second (Fig. 5 right) I-V curves of Fig.1. In Fig.5 left, for positive voltage range, both in the LRS and HRS, drain and gate currents are also equal which suggests a RS filament located close to the drain. In the negative voltage range, during the LRS the filament is still located close to the drain. However, when reset process is produced, and the device reaches the HRS, a RS filament close to the source becomes more relevant. In Fig. 5 right, the filament close to the source is always predominant in all the RS cycle. Then, the results show the existence of conductive filaments close to the drain and source and their dominance depends on the RS cycling. The influence of RS on transistor curves was also studied. Fig. 6 shows that after both set and reset processes, the ID-VG transistor curves are completely distorted and the transistor’s functionality cannot be recovered after reset. Fig 7 shows the ID-VD characteristic of a fresh device (Fig.7A). After forming (Fig.7B), the ID-VD curve is still distinguishable but after set (Fig.7C) the functionality of the device is completely lost and cannot be recovered after reset (Fig.7D). The results suggest that the electrical conditions applied to observe RS in these devices produce severe damage in the dielectric, largely affecting the transistor functionality. Fig 8. shows the four transistor terminals currents registered during the forming process. After forming, source and gate currents have almost the same magnitude suggesting that the location of the RS filament occurs close to the source terminal. This current leakage shifts the ID/VD curve of the transistor being responsible of the negative trend of drain current at low VDS after the forming process (Fig.7B). 5. Conclusions RS phenomenon has been experimentally analyzed in N-type FDSOI quasi-planar NW-FETs with high-k dielectric. Conductive filaments located close to drain and source have been observed; one or the other may control the dielectric conductance, depending on the RS cycling. Although two switchable conductive states can be observed in the MIS gate stack, the electrical conditions used to observe the RS produce severe damage on the transistor functionality. In this regard, future works will explore the possibility of recovering the transistor functionality after a reset process using less harmful RS electrical conditions during the set process. This may allow to combine in a single device a memristor and a transistor [3][7]. Acknowledgements This work was supported by Project PID2019-103869RB-C32 / AEI / 10.13039/501100011033 and PRE2020-092522. EU ASCENT project is acknowledged for sample provision. [1] S.H. Lee, X. Zhu, W. D. Lu, “Nanoscale resistive switching devices for memory and computing applications”, Nano Research, vol. 13, pp. 1228–1243, 2020. [2] S. Poblador, M. Gonzalez, and F. Campabadal, “Investigation of the multilevel capability of TiN−Ti−HfO2−W resistive switching devices by sweep and pulse programming”, Microelectronic Engineering, vol. 187, pp. 148–153, 2018. [3] A. Crespo-Yepes, J. Martin-Martinez, A. Rothschild, R. Rodriguez, M. Nafria and X. Aymerich, "Recovery of the MOSFET and Circuit Functionality After the Dielectric Breakdown of Ultrathin High-k Gate Stacks," in IEEE Electron Device Letters, vol. 31, no. 6, pp. 543-545, 2010. [4] Z. Fang, X. P. Wang, X. Li, Z. X. Chen, A. Kamath, G. Q. Lo, D. L. Kwong, "Fully CMOS-Compatible 1T1R Integration of Vertical Nanopillar GAA Transistor and Oxide-Based RRAM Cell for High-Density Nonvolatile Memory Application," in IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 1108-1113, 2013. [5] X. P. Wan, Z. Fang, X. Li, B. Chen, B. Gao, J. F. Kang, Z. X. Chen, A. Kamath, N. S. Shen, N. Singh, G. Q. Lo, D. L. Kwong, "Highly compact 1T-1R architecture (4F2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation," 2012 International Electron Devices Meeting, San Francisco, CA, USA, 2012, pp. 20.6.1-20.6.4. [6] L. M. Almeida, P. G. D. Agopian, J. A. Martino, S. Barraud, M. Vinet, and O. Faynot, “BackGate bias influence on SOI Ω-gate nanowire down to 10nm width”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016. [7] K.-H. Chuang, E. Bury, R. Degraeve, B. Kaczer, G. Groeseneken, I. Verbauwhede, and D. Linten. “Physically unclonable function using CMOS breakdown position,”, IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2017. Figure 1: 3D sketch of the quasi-planar FD-SOI MOSFET structure (left) and cross-section (right) of the transistor used in this work. Figure 2: Schematic (left) and experimental (right) RS I-V curves in bipolar resistive switching. Figure 3: Biasing configuration of the four device terminals to produce a forming, set and reset processes Figure 4: I-V characteristics measured in the same sample during three consecutive RS cycles, after a forming process. Figure 5: ID (green), IB (blue), IS (red), IG (black) currents, registered during the first (left) and second (right) RS cycles in Fig.1 Figure 6: ID-VG characteristics of the fresh sample (black) and after set (blue) and reset (red) processes. VG = 0,3V 200µ VG = 0,3V 120µ VG = 0,6V VG = 0,6V B) VG = 0,9V VG = 0,9V VG = 1,2V 150µ VG = 1,2V 80µ 100µ A) 40µ Drain Current [A] 0 50µ -40µ 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 800n 4m VG = 0,3V VG = 0,3V VG = 0,6V VG = 0,6V VG = 0,9V 400n VG = 0,9V 2m VG = 1,2V VG = 1,2V 0 0 -400n -2m -800n -4m C) D) -6m -1µ 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Drain Voltage [V] Figure 7: ID-VD transistor characteristics A) for fresh device. B) After forming. After set C) and reset D) processes. Figure 8: ID (green), IB (blue), IS (red), IG (black) currents, registered during forming process.