This is the accepted version of the journal article: Pedreira, Gerard; Martin Martinez, Javier; Crespo Yepes, Albert; [et al.]. «Ran- dom Telegraph Noise and Bias Temperature Instabilities statistical characteriza- tion of -gate FDSOI devices at low voltages». Solid-state electronics, Vol. 209 (November 2023), art. 108735. DOI 10.1016/j.sse.2023.108735 This version is available at https://ddd.uab.cat/record/283178 under the terms of the license Random Telegraph Noise and Bias Temperature Instabilities statistical characterization of Ω-gate FDSOI devices at low voltages G. Pedreira1, J. Martin-Martinez1, A. Crespo-Yepes1, E. Amat1,2 R. Rodriguez1 and M. Nafria1 1 Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) 2 currently with Institute of Microelectronics of Barcelona (IMB-CNM, CSIC) email: javier.martin.martinez@uab.cat 1. Abstract Random Telegraph Noise (RTN) and Bias Temperature Instabilities (BTI) are two mechanisms that can significantly reduce the performance and reliability of integrated circuits. In scaled devices, both phenomena are stochastic, so that a statistical analysis is required to accurately evaluate their impact on a particular technology. This study presents such analysis in scaled FD-SOI devices under various gate and drain voltages, ranging from near-threshold to nominal conditions. The combined effect of RTN and BTI is also modeled in a defect-centric context, and the main impact of the different bias conditions is discussed. 2. Introduction Fully-Depleted Silicon-On-Insulator (FD-SOI) technology has emerged as a promising alternative to conventional CMOS technology due to its ability to improve device performance and reduce process variability [1, 2]. However, the Time-Dependent Variability (TDV) related phenomena that threatens reliability in conventional CMOS devices, such as Random Telegraph Noise (RTN) [3,4] and Bias Temperature Instabilities (BTI) [5,], are still present in high-density FD-SOI devices, emerging as critical issues in these modern technologies [6, 7]. RTN causes fluctuations in the current that can affect device and circuit performance. Moreover, BTI is a degradation of the oxide-channel interface that can reduce the lifetime of FD-SOI devices and affect the long-term reliability of integrated circuits. Nowadays, it is accepted that both RTN and BTI mechanisms share a common origin, i.e., the presence of defects that can trap or release charges, thus altering the functionality of the device, and can be described by defect-centric models such as the Probabilistic Defect Occupancy model [8]. However, the parameter extraction of these models requires high measurement and analysis effort because the number of defects varies from device to device and the probabilities of charge trapping/release is different for each of those defects, being also dependent on external conditions such as applied voltage or temperature. This means that, in nominally identical devices subjected to the same operation conditions, RTN and BTI will impact differently and, therefore, a characterization of the phenomena in a sufficiently large number of devices is needed to carry out statistical analysis and modeling. In this work, FD- SOI devices are characterized under different biasing conditions in order to investigate and model the RTN and BTI effects. From the modeling results, the impact of the different bias conditions on the main physical model parameters is discussed. 3. Experiments and results. The samples used in this study are nMOS Ω-gate FD-SOI Nanowire FETs with 30 nm channel width and 40 nm channel length, fabricated at CEA-LETI. The high-K dielectric stack (HfSiON/TiN) has an EOT=1.3nm, HNW=11nm and the buried oxide (BOX) thickness is 145nm. The average threshold voltage (VT) and nominal operation voltage (VD) are ~0.3V and 1V, respectively. A detailed description of the devices can be found in [9]. For the TDV study, the electrical measurements were performed with a Keithley 4200 Semiconductor Parameter Analyzer (SPA). Several combinations of gate, drain, source and back gate constant voltages were applied (see Table 1). The voltages were applied during 50s, while the drain current was measured. Near- threshold and nominal voltages were selected, to operate the transistor in the linear (VG = 0.3 V) or saturation regimes (VG = 0.5 V and 1 V). For each voltage combination in Table 1, 38 devices were measured. Fig. 1 shows two examples of current traces during the measurements, obtained at two different conditions. Clear charge/discharge events are observed in the top figure, reproducing the RTN behaviour. However, those events are almost hidden by the background noise in the bottom figure and a trend towards lower currents is observed. The shift (if any) in the performance of the devices during the tests was evaluated using the smart procedure described in [8, 10], based on the evaluation of the drain current shift at two different time instants, ΔID=ID(t2)-ID(t1), where t2-t1 is large enough; in this work, t1 = 0s and t2 = 50s (Fig. 1). The observed ΔID can have three different origins: RTN fluctuations, BTI degradation and/or background noise. Those three effects can be modeled together as shown in our previous work [10] and the related model parameters extracted from the experimental data. In our model, the ΔID can be described by eq. (1): 𝛥𝐼 ∑ 𝜂 , 𝑜𝑐 𝑡 𝑜𝑐 𝑡 ∑ 𝜂 , 𝑟𝑎𝑛𝑑𝑛 𝜎 (1) being NRTN and NBTI the number of active defects linked to RTN and BTI, respectively; oci(t) the probability of occupation of the i-th defect at time t; ηRTN and ηBTI the current shifts associated to the RTN and BTI defects and randn(σ) the background noise. Note that NRTN and NBTI can be different for each device, while ηRTN and ηBTI can be different for each defect. This implies that nominally identical devices undergo different variations, which requires considering the statistical distributions of these parameters for an accurate phenomenological modelling. To model the statistical distribution of currents, we assume that NBTI and NRTN follow a Poisson distribution, with mean values and , respectively, while ηRTN and ηRTN follow an exponential distribution with mean values <ηBTI> and <ηRTN>, respectively, as for bulk technologies [3,4]. Notably, these distributions depend on only one parameter, i.e., their mean value. Then, by correctly introducing these four parameters into Eq. 1, it is possible to jointly describe the statistical behavior of RTN and BTI. Furthermore, including sigma in the model allows considering background noise effects into the current shifts. In this context, from traces as those shown in Fig. 1, the cumulative distribution function (CDF) of ΔID is constructed for each of the biasing conditions in Table 1. Fig. 2 shows these CDFs, where it can be observed that the variations of ΔID during the measurement depend on the applied voltage, as the impact of RTN and BTI is strongly dependent on the operating conditions of the devices. All these ΔID distributions have been fitted using eq. 1 by a Monte Carlo approach. Figs. 3 to 5 show some examples of the good fitting to the experimental distributions at several of the biasing conditions. From this fitting, the parameters , , <ηRTN> and <ηBTI>, which account for the statistically distributed number and properties of the defects in the devices, have been extracted. Table 2 shows the complete list of extracted parameters for each test condition, from which several conclusions can be drawn. - For all the studied conditions, RTN is present, as can be deduced from Table 2, where a non-negligible average number of defects () is observed in all cases. However, the differences indicate that RTN depends on the applied voltage. -Similar RTN parameters are obtained for conditions #2 and #3, as the CDFs in Fig. 3 show, suggesting that the back-gate voltage has a negligible effect in the RTN. - The RTN parameters obtained for conditions #1 and #2 point out that increasing VD and VG leads to larger RTN. However, as it will be shown in the following, VG and VD may impact differently on the observed RTN. - The comparison of results obtained at several VD, for the same VG (conditions #2, #4 and #5), suggests that larger RTN effects are observed when the device is operated in saturation. But also, interestingly, for the highest VD, a BTI component also appears (condition #4), even when the device is operated within the nominal voltage range (note that accelerated stress test conditions are not applied). - The RTN parameters at conditions #5 and #6 show that VG has a larger impact in RTN since, despite the low VD, a large RTN component is measured (the largest <ηRTN> is obtained for VG = 1V, VD = 0.05V). Moreover, BTI is larger (i.e., larger and <ηBTI>) than when a large VD is applied (condition #4, VG=0.5V, VD=1V). This is observed in Figure 4, where the BTI component shows the largest negative current shifts for the largest VG. - The exchange of drain and source, either when in the linear (conditions #5 and #8) or saturation (conditions #2 and #7) regimes, shows no remarkable differences (Fig. 5), which suggests that, at these low voltages, RTN defects are quite uniformly distributed along the channel. 4. Conclusions This study presents a statistical characterization of Ω-gate FDSOI NWFETs measured under various biases (near-threshold and nominal) and operating conditions (linear and saturation), interpreted within a defect- centric model. The statistical analysis of the measurements and the model parameters extracted indicate that, in this voltage range, RTN is the dominant TDV mechanism, although BTI can also be observed under nominal conditions. Regarding the RTN effects, (i) body bias has a negligible impact, (ii) the effects are more pronounced in the saturation regime, and (iii) VG has a greater impact on the observed RTN than VD. The understanding of TDV impact and its modelling is crucial for designing reliable circuits, and this study aims to contribute towards this goal in the context of FD-SOI technologies. Acknowledgements This work was supported by grant PID2019-103869RB-C32, funded by MCIN/AEI/ 10.13039/501100011033. G. Pedreira was supported by the scholarship BES-2017-081462. EU ASCENT project is acknowledged for sample provision. [1] J. Mäkipää and O. Billoint, "FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?," 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013, pp. 554-557, doi: 10.1109/ISCAS.2013.6571903. [2] G. Jacquemod et al., "Study and reduction of variability in 28 nm FDSOI technology," 2015 International Workshop on CMOS Variability (VARI), Salvador, Brazil, 2015, pp. 19-22, doi: 10.1109/VARI.2015.7456557. [3] H. Miki et al., "Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty," 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, USA, 2012, pp. 137-138, doi: 10.1109/VLSIT.2012.6242499. [4] G. Pedreira et al., "A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices," 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2019, pp. 1-5, doi: 10.1109/IRPS.2019.8720582. [5] B. Kaczer et al., "Origin of NBTI variability in deeply scaled pFETs," 2010 IEEE International Reliability Physics Symposium, Anaheim, CA, USA, 2010, pp. 26-32, doi: 10.1109/IRPS.2010.5488856. [6] P. Srinivasan, D. Song, D. Rose, M. LaCroix and A. Dasgupta, "Back gate bias effect and layout dependence on Random Telegraph Noise in FDSOI technologies," 2021 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405199. [7] N. Choudhury, N. Parihar, N. Goel, A. Thirunavukkarasu and S. Mahapatra, "Modeling of DC - AC NBTI Stress - Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 1281-1288, 2020, doi: 10.1109/JEDS.2020.3023803. [8] J. Martin-Martinez et al., "Probabilistic defect occupancy model for NBTI," 2011 International Reliability Physics Symposium, Monterey, CA, USA, 2011, pp. XT.4.1-XT.4.6, doi: 10.1109/IRPS.2011.5784605. [9] L. M. Almeida, P. G. D. Agopian, J. A. Martino, S. Barraud, M. Vinet, and O. Faynot, “BackGate bias influence on SOI Ω-gate nanowire down to 10nm width”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016. [10] G. Pedreira, J. Martin-Martinez, P. Saraza-Canflanca, R. Castro-Lopez, R. Rodriguez, E. Roca, F.V. Fernandez, M. Nafria, Unified RTN and BTI statistical compact modeling from a defect-centric perspective, Solid-State Electronics, Volume 185, 2021, 108112, ISSN 0038-1101, https://doi.org/10.1016/j.sse.2021.108112. Figures and tables: Biasing Conditions Condition Nº Vgate Vdrain Vsource Vback gate (V) (V) (V) (V) 1 0.3 0.3 0 0 2 0.5 0.5 0 0 3 0.5 0.5 0 -15 4 0.5 1 0 0 5 0.5 0.05 0 0 6 1 0.05 0 0 7 0.5 0 0.5 0 8 0.5 0 0.05 0 Table 1: Combinations of drain/gate/source/back gate voltage used to evaluate the RTN and BTI impact on the drain current shift. Model Parameter Condition Nº <𝜂 > <𝜂 >(nA) (nA) 1 0.97 1.09 - 2 6.46 8.01 - - 3 7.10 7.90 - - 4 9.69 7.71 0.05 5.20 5 5.61 2.67 - - 6 4.36 14.83 0.55 9.96 7 9.44 4.52 - - 8 6.89 1.88 - - Table 2: Average values of the model parameters obtained from the fitting of the ΔID CDFs (as those in Figs. 2 to 5) to eq. (1), for the different experimental conditions in Table 1. Figure 1: Examples of experimental ID current traces measured at two different conditions (#2 and #6 in Table 1). (top) RTN is dominant. (bottom) BTI and RTN are simultaneously observed. For the determination of the defect-centric model parameters, the current shift is evaluated as the difference of the currents measured at two given time instants. In our case, t1=0s and t2=50s Experimental Cumulative Distribution Funtion 100 Bias Conditions Vg=0.3,Vd=0.3 Vg=0.5,Vd=0.5 80 Vg=0.5,Vd=0.5 Vbg=-15 Vg=0.5,Vd=1 Vg=0.5,Vd=0.05 Vg=1,Vd=0.05 Probability (%) 60 Vg=0.5,Vs=0.5 Vg=0.5,Vs=0.05 40 20 0 -100 -80 -60 -40 -20 0 20 40 60 Current Shift (nA) Figure 2: Experimental CDFs of the current shifts (ΔID) measured for all the biasing conditions. Figure 3: CDFs of the current shifts obtained with and without back bias (conditions #2 and #3). Symbols show the experimental data and continuous lines their fitting. Figure 4: CDFs for the cases where a BTI component is observed, which correspond to either a ‘large’ VG or VD (conditions #4 and #6). The BTI degradation is larger for the VG = 1 V case (blue curve/squares). Symbols show the experimental data and continuous lines their fitting. Figure 5: CDFs of the current shifts measured when source and drain are exchanged, and the device is operated in saturation (conditions #2 and #7). Symbols show the experimental data and continuous lines their fitting.