sensors Article Dual-Gate Organic Thin-Film Transistor and Multiplexer Chips for the Next Generation of Flexible EG-ISFET Sensor Chips Ashkan Rezaee * and Jordi Carrabina Department of Microelectronic and System, Autonomous University of Barcelona, 08193 Barcelona, Spain; jordi.carrabina@uab.cat * Correspondence: ashkan.rezaee@uab.cat Abstract: Ion-sensitive field-effect transistors (ISFETs) are used as elementary devices to build many types of chemical sensors and biosensors. Organic thin-film transistor (OTFT) ISFETs use either small molecules or polymers as semiconductors together with an additive manufacturing process of much lower cost than standard silicon sensors and have the additional advantage of being environmentally friendly. OTFT ISFETs’ drawbacks include limited sensitivity and higher variability. In this paper, we propose a novel design technique for integrating extended-gate OTFT ISFETs (OTFT EG-ISFETs) together with dual-gate OTFT multiplexers (MUXs) made in the same process. The achieved results show that our OTFT ISFET sensors are of the state of the art of the literature. Our microsystem architecture enables switching between the different ISFETs implemented in the chip. In the case of sensors with the same gain, we have a fault-tolerant architecture since we are able to replace the faulty sensor with a fault-free one on the chip. For a chip including sensors with different gains, an external processor can select the sensor with the required sensitivity. Keywords: OTFT; EG-ISFET; multiplexer; dual-gate OTFT; electrostatic discharge 1. Introduction Thin-film transistor (TFT) technology has advanced significantly and has been widely Citation: Rezaee, A.; Carrabina, J. employed in many fields since the creation of the first TFT in 1962 [1–3]. The fast advance- Dual-Gate Organic Thin-Film ment of liquid crystal display (LCD) technology in the 1970s presented new opportunities Transistor and Multiplexer Chips for for TFTs. TFTs were best suited to fulfill the LCD industry’s urgent need for a semiconduc- the Next Generation of Flexible EG-ISFET Sensor Chips. Sensors 2023, tor switch device that could drive a big-area active matrix (AM) on glass [4]. As a result of 23, 6577. https://doi.org/10.3390/ this urge, amorphous silicon (a-Si)-based TFT devices were introduced by Le Comber et al., s23146577 to be used in AM LCD (AMLCD) in 1979 [5]. A year later, hydrogenated a-Si (a-Si:H) met the demand of AMLCD since its mobility improved significantly [6]. Academic Editor: Min Zhang TFT technology has advanced continuously along with the growth of flat panel dis- Received: 15 June 2023 play (FPD) technology, which employed the TFT as its fundamental component. This Revised: 10 July 2023 lead to a technology evolution similar to silicon, with a main focus on size rather than Accepted: 17 July 2023 integration density. Published: 21 July 2023 The mobility of an a-Si:H TFT is insufficient for the FPD devices, which need a higher TFT mobility to optimize driving performance. In 1980, Depp et al., illustrated that poly- crystalline silicon (p-Si) TFT devices, with a typical carrier mobility of 102 cm2 V−1 s−1 , are an excellent alternative for meeting high-resolution and huge-current driving demands [7]. Copyright: © 2023 by the authors. Even though TFT mobility reached 50 cm2 V−1 s−1 , the process temperature of more than Licensee MDPI, Basel, Switzerland. 300 ◦ C severely limited its practical application. As a result, many procedures for producing This article is an open access article low-temperature polysilicon were tested (LTPS) [8]. Serikawa et al., were the first to use distributed under the terms and laser irradiation to lower the annealing temperature of polysilicon in 1989 [9]. However, conditions of the Creative Commons the commercial promotion of TFTs was constrained because it needed to be annealed at Attribution (CC BY) license (https:// 300 ◦ C to obtain solid results. By lowering the LTPS process temperature to less than 150 ◦ C, creativecommons.org/licenses/by/ LTPS TFT arrays could be manufactured on the same glass substrate as amorphous Si TFT 4.0/). Sensors 2023, 23, 6577. https://doi.org/10.3390/s23146577 https://www.mdpi.com/journal/sensors Sensors 2023, 23, 6577 2 of 22 arrays [10]. When compared to an a-Si:H TFT, the carrier mobility of an LTPS TFT can be tens to hundreds of times greater. The advantages of LTPS LCDs over conventional a-Si:H LCDs include quick response times, excellent resolution, and high aperture ratio. With the advancement of internet of things (IOT) technology in recent years, TFT arrays have also been used in the low-cost IC industry. Biggs et al., published a 32-bit ARM (a reduced instruction-set computing architecture) microprocessor constructed with metal-oxide TFT technology on a flexible substrate in 2021, paving the way for the development of low-cost, fully flexible, smart integrated systems [11]. Many different novel materials have been utilized in attempts to make TFTs in addition to the traditional silicon-based technologies. Organic semiconductors (OSCs) are the one among them that have been the subject of the most research. Flexible electronics need transistors that work well under a specific range of mechanical deformation, and OSCs seem to be one of the best options for these semiconductors. The first organic thin-film transistor (OTFT), which used polyacetylene as the semi- conductor, was described by Ebisawa et al. in 1983 [12]. Drury et al., developed flexible polyimide substrates for all-polymer integrated circuits in 1998 [13]. The OTFT device offers numerous advantages, including low cost, structural flexibility, and big-area fabrication based on a solution technique, but it is insufficient in performance uniformity and device stability [14–16]. As a result, the OTFT has the potential to be employed in a wide variety of applications, including electrophoretic displays, radio frequency identification (RFID), and biomedical sensors [17–21]. Furthermore, OTFTs may be used in the driving array of mini-LED backlight sources. Massive efforts in material chemistry and processing techniques have been made in recent decades to improve the device mobility of OTFTs [22–27]. In many envisioned power-constrained electronic systems, reducing leakage current is equally or even more critical [28]. The quality and thickness of the Organic Gate Insulator (OGI) layer determine how much leakage occurs through it, and patterning the OSC layer can efficiently control parasitic leakage out of the channel region [29–31]. The primary obstacle to be overcome is the intrinsic channel leakage current, which is contributed by small carrier injection from the drain contact [32]. The carrier mobility (µ) of OTFTs has now surpassed 2 cm2 V−1 s−1 , above that of amorphous silicon transistors (1 cm2 V−1 s−1 ) [33–36]. However, considering the need of high-resolution displays, it is still lower than inorganic semiconductor materials like LTPS TFTs and oxide semiconductors like IGZO TFTs [37–39]. As a result, effectively boosting output current and improving reliability are critical concerns for OTFT commercialization. Using a common p-type device as an illustrative example, minority carrier electrons might be injected from the drain electrode into the lowest unoccupied molecular orbital (LUMO) states of the OSC with the application of a moderately positive gate voltage for the OFF-state or deep subthreshold regime. For narrow energy bandgap (Eg) OSCs, such as donor-acceptor (D-A) structure molecules, which have been extensively researched for high mobility because of their strong intermolecular contacts permitting efficient intermolec- ular charge transport, the minority carrier injection is more severe [40,41]. Performance instability was also brought on by the trapped electrons in the OSC layer or at the inter- faces [42,43]. In order to reduce the negative consequences of minority carrier injection, two different types of techniques have been developed (electrons in p-type OTFTs) [44–48]. One method is to add molecular additives to the channel as specific charge-carrier electron traps, which prohibit the injected electrons from assisting in conduction [45,46]. However, it is challenging to manage this approach in processes for complete electron avoidance without interfering with the transit of holes in the ON-state [49]. The other technique is to limit electron injection by increasing the height of the electron injection barrier by contact doping or adding a broad interfacial layer at the contact interface [44,47,48]. The relatively poor charge-transfer doping achieved in OSCs, unlike that obtained with inorganic semi- conductors, is not able to completely eliminate electron injection, and the dopants in the form of small-molecule counterions may migrate throughout the OSC layer, leading to device instability [50,51]. Sensors 2023, 23, 6577 3 of 22 In this paper, for OTFTs, we propose to follow the same evolution that led from stan- dard MOS transistors to build silicon MOS ISFETs using standard fabrication processes [52]. As was the case for silicon CMOS transistors, some changes must be made in the process technology to implement microsystems including sensors and circuitry. In our case, since we plan to use an extended gate, the required modification is the capability to change the threshold voltage. This is obtained from a dual-gate technology. 2. EG-ISFET Sensors Microfluidics is a burgeoning area of study that deals with the microscale treatment of fluids; it is most often distinguished by objects that have critical dimensions less than 1 mm. Researchers can use a variety of physical laws that scale well at this scale, including quick diffusion [53], laminar flows [54], Dean flow [55], rapid heat transport [56], and taking advantage of the high surface area to volume ratio [57]. Microfluidics is used in a wide range of industries, including analytical chemistry [56], molecular biology [58], energy production [59], cell separations [55], and energy generation. A large portion of the work on the subject of microfluidics has been carried out utilizing soft lithography, which Whitesides [60] first developed in 1998. Soft lithography techniques, particularly for polydimethylsiloxane (PDMS), have been extensively studied [61,62]. The need for cleanroom manufacturing, while well-developed by the microelectromechanical systems (MEMS) community, is still expensive and time-consuming, and this was one of the key challenges of soft lithography in the beginning. Recently, this has been somewhat mitigated by low-cost mold-making techniques, as discussed by Faustino [63]. In addition to soft lithography, other fabrication techniques for submillimeter channels have been developed by microfluidic engineers for several reasons, including lower costs, quicker turnaround times, less expensive materials and tools, and improved functionality. One way to measure pH levels of microfluidics systems is using ion-sensitive field- effect transistors (ISFETs). ISFETs are a type of sensor that can detect changes in ion concentrations, including hydrogen ions (H+ ), which are responsible for pH. The ISFET consists of a thin film of metal oxide that acts as the sensing element and is placed near the gate of a field-effect transistor (FET). The FET modulates its threshold voltage in response to changes in the concentration of ions in the film, allowing for the detection of pH levels [64–66]. When monitoring electrochemical reactions, ISFETs have many benefits. ISFETs can be mass produced and further integrated into other sensing systems because they are based on the common complementary metal-oxide-semiconductor technique [64–68]. ISFETs can be implemented with OTFTs by connecting the top-gate electrode to the media where the pH measurement must be performed. In this way, the drain to source current will depend on the electrical charge related to the pH. Furthermore, pH electrode and gate electrode can be separated (while connected with a good conductor) to produce the extended-gate electrode. This allows for an easier integration of the electrode with the measurement environment and increases the level of reuse of the ISFET sensors, which are more expensive than electrodes and can trap chemical materials that degrade their behavior. Ion-sensitive field-effect transistors with extended gates are known as EG-ISFETs. They are a particular kind of sensor that can determine the number of ions present in a solution by observing changes in the surface potential of a sensing oxide layer [69]. By adopting an extended conductive layer to separate the sensing oxide layer from the gate oxide of a thin-film transistor (TFT), the gate oxide is shielded from the electrolyte solution and the sensor’s stability and robustness are increased. Many applications, including biosensors, environmental monitoring, and food quality management, are possible with EG-ISFET sensors [70]. The simultaneous detection of multiple analytes in a single sample can be obtained by using several electrodes with different sensitive materials acting as a microelectrode array (MEA) on several EG-ISFETs. The multiplexing capabilities of EG-ISFETs makes them an effective tool for monitoring pH levels in cells as well as other ionic species. Sensors 2023, 23, 6577 4 of 22 The EG-ISFET has been used in a variety of applications, including the measurement of pH levels in cells, tissues, and biofluids [70–73]. It has been used in cancer cell research, where changes in pH levels can indicate the presence of cancerous cells [73]. It has also been used in stem cell research, where pH levels are used to monitor stem cell differentiation into specific cell types [74,75]. In addition to its use in medical applications, the EG-ISFET has also been used in environmental monitoring, where it can be used to measure pH levels in water and soil [76,77]. The EG-ISFET has also been used in food safety applications, where it can be used to detect the presence of harmful bacteria in food products [77]. 3. Dual-Gate OTFT Technology Modern IC fabrication in CMOS technology nodes requires a lot of power and has a significant environmental impact [78]. SmartKem offers a more energy-efficient and eco- friendly process that involves organic materials and fewer fabrication steps than CMOS, which reduces cost and greenhouse emissions. The reduction of the complete fabrication process temperature from 180 ◦ C to 80 ◦ C has recently been demonstrated [79]. This ecofriendly fabrication process will: (1) require overall lower energy use in manufacturing (since no PECVD is required); (2) use a wider choice of plastics with improved properties concerning transparency, biodegradability (<12 months), bio-derived (e.g., cellulose), and low cost; and (3) be able to be integrated with other processes without destroying their devices (e.g., an OTFT backplane could be processed on top of the OLED device), which will also provide the potential for R2R manufacturing. This is one of the reasons to select the SmartKem OTFT low-temperature process to implement our integrated microsystems. Their spin-coated OTFT devices have mobilities of 2.5 cm2 V−1 s−1 in a short channel (down to a channel length of 2.5 microns), low variability (<10%), and the option to turn on a voltage of +2 V to +4 V (on single-gate transistors). The process also enables digital design on OFETs (organic field-effect transistors) with non-complimentary logic and 3.3 V power supplies (or above). SmartKem devices can be fabricated on rigid (usually glass) or flexible (usually PEN) surfaces. OTFT devices on flexible substrates show good performance with bending [80] that allows for adapting their sensors and circuits to different environments (wearables, industrial, etc.). A less than 18% positive VT shift in OTFT devices is observed under differ- ent bending conditions. This degradation comes from two mechanisms: the contribution of oxygen for a positive VT shift and the contribution of mechanical tensile bending stress for a negative one. The main difference in degradation is the change in the molecular distance due to different bending conditions (tensile/compressive). One method to lower electron injection by raising the height of the electron injection barrier is the dual-gate structure. The electrons can be repelled from the OSC layer, and the leakage current can be reduced by applying a negative voltage to the back gate [81–83]. SmartKem also introduced dual-gate OTFTs processing steps on their single-gate OTFT process, similar than other organic processes that implement digital circuitry [84,85]. In our case, these transistors play a crucial role in ensuring that the analog multiplexers effectively block the current from the unselected ISFET sensors [86,87]. The dual-gate structure consists of five metal masks, as shown in Figure 1. The structure is provided by SmartKem Co., (Manchester, UK). In this strategy, the first mask is used to sputter and shape Mo/Al/Mo back-gate metal by photolithography and wet etching with the thicknesses of 11 nm/70 nm/60 nm (Figure 1a). The back-gate layer was then spin-coated with the base layer, which was then UV-cured (Figure 1b). This layer has a thickness of about 0.5 um. The second mask is devoted to gold deposition for the source and drain metals, is roughly 50 nm thick, and is photolithographically patterned (Figure 1c). Their single gate-OTFT process starts directly in step (c), involving the deposition and patterning of the source and drain metals. Sensors Sensors2023, 2023,23, 23,x6577 FOR PEER REVIEW 5 5ofof22 22 (a) (b) (c) (d) (e) (f) (g) (h) (i) Figure Figure1.1.Different Differentsteps steps of of SmartKem SmartKem fabrication process: (a) Fabrication of first first layer layer (Mo/Al/Mo (Mo/Al/Mo back-gate back-gatemetal) metal)by bysputtering, sputtering,photolithography, photolithography, and and wet-etching wet-etching (thickness: (thickness: 11 11 nm/70 nm/70nm/60 nm/60nm). nm). (b) Spin-coating and UV/thermal curing of base layer. (c) Sputtering, photolithography (b) Spin-coating and UV/thermal curing of base layer. (c) Sputtering, photolithography and wet- and wet- etching of second metal layer. (d) Spin-coating and baking of SAM and OSC layers (thickness: 30 etching of second metal layer. (d) Spin-coating and baking of SAM and OSC layers (thickness: nm OSC). (e) Spin-coating and baking of OGI layer, spin-coating and UV/thermal curing of SRL 30 nm OSC). (e) Spin-coating and baking of OGI layer, spin-coating and UV/thermal curing of SRL layer (thickness: 150 nm OGI and 400 nm SRL). (f) Sputtering, photolithography and wet-etching of layermetal third (thickness: 150 nm OGI layer (thickness: 50and 400 nm). (g)nm SRL). (f) Sputtering, Spin-coating photolithography and UV/thermal and wet-etching curing of passivation layer of third metal layer (thickness: 50 nm). (g) Spin-coating and UV/thermal (thickness: 2 um). (h) Patterning of passivation layer using photoresist and dry-etch curing of transfer. passivation (i) layer (thickness: Sputtering, 2 um). (h) Patterning photolithography of passivation and wet-etching layer using photoresist and dry-etch transfer. of fifth layer. (i) Sputtering, photolithography and wet-etching of fifth layer. The second mask is devoted to gold deposition for the source and drain metals, is roughlyGate50layer fabrication nm thick, and is involves several stages.patterned photolithographically Self-assembled (Figuremonolayers (SAM) 1c). Their single and gate- organic OTFT semi-conductors process starts directly (OSC) with(c), in step a 30involving nm thickness are spin-coated the deposition and bakedof and patterning asthe the initial stage (Figure source and drain metals. 1d). Next,layer Gate the Organic fabricationGate Insulator involves (OGI); several dielectric stages. sputter-resistant Self-assembled layer (SRL), monolayers (SAM)which and organic semi-conductors (OSC) with a 30 nm thickness are spin-coated and baked1e). is an acrylate-based dielectric; spin-coating; and UV curing were applied (Figure The as the thicknesses of the initial stage (Figure 1d). OGI and SRL were 150 nm and 400 nm, respectively. Then, mask 3 was Next, used, thefollowed by a photolithographic pattern (Figure 1f). All additional Organic Gate Insulator (OGI); dielectric sputter-resistant layer (SRL), which OGI, SAM, SPL, and OSC were eliminated using mask 3 (Figure 1g). This layer was around 50 nm is an acrylate-based dielectric; spin-coating; and UV curing were applied (Figure 1e). The thick. The remaining region was then spin-coated with the passivation layer at a height thicknesses of the OGI and SRL were 150 nm and 400 nm, respectively. Then, mask 3 was of 2000 nm (Figure 1h). With the use of mask 4, the passivation layer copies the design used, followed by a photolithographic pattern (Figure 1f). All additional OGI, SAM, SPL, using photoresist patterns. Finally, mask 5, also known as gate-contact metal, was used for and OSC were eliminated using mask 3 (Figure 1g). This layer was around 50 nm thick. patterning sputtered gold, and was wet-etched in a technique identical to that used with The remaining region was then spin-coated with the passivation layer at a height of 2000 the previous metal layers (Figure 1i). nm (Figure 1h). With the use of mask 4, the passivation layer copies the design using pho- Electrostatic discharge (ESD), which can result in a very high current passing through toresist patterns. Finally, mask 5, also known as gate-contact metal, was used for pattern- the device or microchip in a very short amount of time and cause catastrophic irreparable ing sputtered gold, and was wet-etched in a technique identical to that used with the pre- damage, is one of the most common risks to the dependability of electronic components. In vious metal layers (Figure 1i). everyday life, electrostatic discharge (ESD) is a common occurrence. When two different- Electrostatic charged objects are discharge near one(ESD), which another, the can result electric in aeither field very high causescurrent passing through the insulating medium the device or microchip in a very short amount of time and cause between them to break down and create a conductive path, neutralizing the charge catastrophic irreparable transfer; damage, is onethe alternatively, of the most common objects different-charged risks todirectly the dependability contact oneofanother, electronic components. neutralizing the In everyday charge life, When transfer. electrostatic discharge a conductive path (ESD) is a common is created, occurrence. ESD happens [88]. When two differ- ent-charged objects are Silicon-based nearsuffer ISFETs one another, from ESD the electric (on thefield either causes sensitive-gate the insulating electrode), me- so silicon dium between substrates allowthem to break protection for building down and circuits create aforconductive path, neutralizing their input-output pins (usingthediodes chargeto transfer; alternatively, the different-charged objects directly contact connect the external inputs to the voltage supply sources). The substrates used for TFTsone another, neutral- izing the charge and OTFTs, transfer. especially When those a conductive facing path isare flexible systems, created, ESD usually happensand dielectrics [88]. do not offer Silicon-based ISFETs suffer from ESD (on the possibility to implement these circuits based on diodes. the sensitive-gate electrode), so silicon sub- strates allow for building protection circuits for their input-output pins (using diodes to Sensors 2023, 23, 6577 6 of 22 From the circuit point of view, one technique to gain fault-tolerance against ESD is to add redundancy. The ISFET destroyed by ESD can be substituted by another one in the same chip without the need to change the chip itself—just by correctly reconfiguring it. The low cost of OTFTs processes allow for integrating several devices in the same chip/die at a reduced cost increase. For our study, we selected a substrate die size to fit one standard silicon chip package to demonstrate our concept while minimizing human contact when handling dies. A QFN64 package with a 9 mm × 9 mm area dimension and 64 pins defines the design die and allows for shielding it from ESD and light effects on OTFTs. Further flexible implementations will allow for these protections on encapsulations and substrates. 3.1. Corbino-Shape Transistors Circular-shaped transistors, also known as Corbino transistors, are less frequently employed in circuit designs; instead, this gate shape is more frequently used in the display field to open or close a light-emitting diode (LED). The channel in this transistor architecture is shaped like a ring. The Corbino disk, first reported by M. Corbino in 1911, is a disk with inner and outer concentric ring contacts [89]. It has been primarily used in magneto- resistance measurements [90] and has more recently been adopted for organic thin-film transistor (TFT) architectures [91,92]. An annular-shaped electrode was initially used in 1996 in hydrogenated amorphous silicon (a-Si:H) TFTs to give a lower gate-to-source capacitance and a lower photocurrent level in active-matrix liquid crystal displays (AM-LCDs) [93]. Ring-shaped and circular electrodes were utilized in a pseudometal-oxide semiconductor field-effect transistor in 1999 to describe the electrical properties of silicon-on-oxide wafers by device geometrical features [94]. For a given transistor width, the Corbino TFT’s circular channel design reduces the drain capacitance and resistance. By decreasing the impacts of parasitic capacitance and boosting switching speed and frequency response, this improves the device’s perfor- mance [95,96]. Furthermore, its circular symmetry produces a less variable behavior of OTFT organic semiconductors. The Corbino TFT is appropriate for sensors and other high-speed signal processing applications. In order to prevent the direct current (DC) component of the input signal from having an impact on the output signal, the suggested sensor makes use of the Corbino TFT. The sensor’s operational point is set to the desired value by supplying a bias voltage to the Corbino TFT’s gate terminal [95]. As a result, the input signal may be measured by the sensor more precisely and steadily. Because of its distinctive circular form and low drain capacitance, the Corbino TFT is able to detect signals regardless of the input signal’s DC component. It also has a high switching speed. One example of such an application is a large-area active-matrix organic light-emitting diode (AMOLED) display pixel [97]. 3.2. Interdigitated Transistors The inverted/staggered and co-planar OTFT structures are the most widely used devices when looking for large transistor width [14]. Interdigitated electrodes are often used to compensate for the low OSC conductivity in OTFTs. The source and drain electrodes have a comb-like shape and their teeth are alternately interlocked with each other. This increases the channel width per unit of area and allows higher current density [98]. Maximizing the transistor width per unit of area allows us to place more transistors on the same substrate. However, this geometry still has some limitations in terms of performance, as it depends on the careful alignment of OSC crystals along the Drain and Source (D/S) electrodes during OSC deposition. This involves using a nitrogen flow, changing the temperature, and adjusting the solvent type and ratio [99–101]. Sensors 2023, 23, x FOR PEER REVIEW 7 of 22 Sensors 2023, 23, 6577 (D/S) electrodes during OSC deposition. This involves using a nitrogen flow, changing7 the of 22 temperature, and adjusting the solvent type and ratio [99–101]. 4.4.Microsystems MicrosystemsChip ChipArchitecture Architecture Our Our microsystemsarchitecture microsystems architecturemerges mergesseveral severalEG-ISFET EG-ISFETsensors sensorsimplemented implementedwith with dual-gate dual-gate OTFTs with analogue OTFT multiplexers in the same chip, toselect, OTFTs with analogue OTFT multiplexers in the same chip, to select,through throughaa digital digitalcontrol, control,the thesensor sensorthatthatwill willbebeused usedforforthe the measurements. measurements.The Themain maingoal goalofofthis this integration integrationisistotoenhance enhancethe thereusability reusabilityofofchips chipsbybyselecting selectingamong amongseveral severalISFET ISFETsensors sensors without withoutthe theneed needtotochange changethe thechip. chip. The Thesystem systemarchitecture architectureisisillustrated illustratedin inFigure Figure2,2,in inwhich whichour ourchip chipwill willbe beconnected connected to:(i) to: (i)the theextended extendedgate gate and and external external electrode modules modules (left (left side); side);and and(ii) (ii)aaMicrocontroller Microcontrol- Unit ler Unit(MCU) (MCU)unit thatthat unit willwill manage managethe the control andand control biasbias of the of chip (and(and the chip external electrode) external elec- and will trode) andreceive the analog will receive signalsignal the analog from thefromISFETs (routed the ISFETs by the by (routed multiplexers). the multiplexers). Systemarchitecture Figure2.2.System Figure architectureshowcasing showcasingthe theintegration integrationof ofaapair pairof ofISFETs ISFETsand andone oneMUX MUX(one (onechip chip section) section)and andits itsconnection connectiontotoexternal externalcomponents components(external (externalelectrodes electrodes and and MCU). MCU). 5.5.Multiplexing MultiplexingSensorSensorSignal Signal Analoguemultiplexers Analogue multiplexersare areelectronic electronicdevices devicesthat thatselect selectone oneinput inputsignal signalfrom frommany many and route it to a single output. They are widely used in a wide range of and route it to a single output. They are widely used in a wide range of applications, in- applications, in- cluding data acquisition systems, signal processing, and communication cluding data acquisition systems, signal processing, and communication systems [102– systems [102–107]. Analogue multiplexers can be built with a variety of technologies, including bipolar junc- 107]. Analogue multiplexers can be built with a variety of technologies, including bipolar tion transistors (BJTs), field-effect transistors (FETs), metal oxide semiconductors (MOS) junction transistors (BJTs), field-effect transistors (FETs), metal oxide semiconductors and OTFTs. Because of their distinct properties, OTFTs are a particularly appealing solution (MOS) and OTFTs. Because of their distinct properties, OTFTs are a particularly appealing for multiplexer applications. solution for multiplexer applications. A common approach for utilizing ISFET arrays is to employ MUXs and connect them A common approach for utilizing ISFET arrays is to employ MUXs and connect them to a microcontroller unit (MCU), as demonstrated in Figure 3 [102]. A series of select lines to a microcontroller unit (MCU), as demonstrated in Figure 3 [102]. A series of select lines controls the matrix, which is used to pick the chosen input signal. The selected signal is controls the matrix, which is used to pick the chosen input signal. The selected signal is then routed to the output after passing through a buffer amplifier. then routed to the output after passing through a buffer amplifier. One of the most difficult tasks in constructing an analogue multiplexer employing One of the most difficult tasks in constructing an analogue multiplexer employing OTFTs is minimizing crosstalk between neighboring input signals [108,109]. The current OTFTs is minimizing crosstalk between neighboring input signals [108,109]. The current running through one channel impacts the voltage at the input of an adjacent channel due to running through one the low impedance channelcloser between impacts the voltage electrical nodes.atThis the is input of antoadjacent referred channel as crosstalk. Thisdue can to the low impedance between closer electrical nodes. This is referred to as result in a loss in signal quality and a decrease in the multiplexer’s overall performance. crosstalk. This can result When in compared a loss in signal quality and to standard a decrease transistors, silicon-based in the multiplexer’s the usageoverall performance. of OTFTs in multi- When compared to standard silicon-based transistors, the usage plexer circuits allows for low-noise operation, good signal quality, and improved of OTFTs in multi- perfor- plexer circuits allows for low-noise operation, good signal quality, and mance [110]. To provide best performance, the design of an analogue multiplexer based onimproved perfor- mance OTFTs[110]. must To provide consider best performance, crosstalk the designinput between neighboring of ansignals. analogue multiplexer based on OTFTs must consider crosstalk between neighboring With the continuous growth of OTFT technology and the input signals. development of new ap- proaches for avoiding crosstalk, we may expect to see an increase development With the continuous growth of OTFT technology and the in the number of of new ap- analogue proaches for avoiding crosstalk, we may expect to see multiplexer applications that use OTFTs in the future [111,112]. an increase in the number of ana- logue multiplexer applications that use OTFTs in the future [111,112]. Sensors 2023, 23, x FOR PEER REVIEW 8 of 22 Sensors2023, Sensors 2023,23, 23,6577 x FOR PEER REVIEW 88 of of 22 22 Figure Figure3.3. System-level 3. System-level architecture System-level architecture with architecturewith focus withfocus on focuson module onmodule interconnections moduleinterconnections and interconnectionsand components. andcomponents. components. Figure 6. 6. Circuit Design 6. Circuit Circuit Design Design Next, Next, Figure 44 shows the schematic circuit implemented in our chips according to the Next, Figure Figure 4 shows shows the the schematic schematic circuit circuit implemented implemented inin our our chips chips according according to to the the architecture architecture presented in Figure 2. All OTFTs are dual-gate but they will be implemented architecture presented presented inin Figure Figure 2. 2. All All OTFTs OTFTs are are dual-gate dual-gate but but they they will will be be implemented implemented using using different topologies, as shown in Table 1. using different different topologies, topologies, asas shown shown inin Table Table 1. 1. Figure Figure 4.4. Figure OTFT 4. OTFT schematic OTFT schematic of schematic of eight of eight of eight of our ofour sensor oursensor chips. sensorchips. The chips. The chip The chip contains chip contains eight contains eight similar eight similar structures similar structures structures implemented implemented implementedwithwith different withdifferent variants differentvariants (transistor variants(transistor shape, (transistorshape, dimension, shape,dimension, etc.). dimension,etc.). Control etc.). Control signals Controlsignals (CS signals (CS and (CS and !CS) and !CS) !CS) are provided areprovided are providedbyby external byexternal MCU. externalMCU. MCU. Our Our design Ourdesign strategy designstrategy employs strategyemploys employstwo two two different different different types types of of transistors of transistors types for for transistors its its further its further for evalua- evaluation: further evalua- tion: interdigitated interdigitated transistors transistors and and Corbino Corbino transistors, transistors, bothboth of of various various sizes. sizes. The The tion: interdigitated transistors and Corbino transistors, both of various sizes. The Corbino Corbino Corbino transistors transistors were transistors were built built in built inparallel in parallelto parallel totoincrease increasethe increase equivalent the the equivalent equivalent gain gain gain (W/L) (W/L) (W/L) for for this for type this of of tran- this type type of tran- sistor (explained transistor in (explained more in detail more in detail theinfollowing the paragraphs). following The paragraphs). overall The function overall sistor (explained in more detail in the following paragraphs). The overall function of the of functionthe Sensors 2023,23, Sensors2023, 23,6577 x FOR PEER REVIEW 9 of 9 of 2222 of the circuit circuit can becan be impacted impacted by theby the performance performance characteristics characteristics that different that different transistor transistor sizes sizes may display. may display. Hence, Hence, to maketo make sure thesure the circuit circuit satisfiessatisfies the specifications, the specifications, the study the careful careful study and selection and selection of the suitable of the suitable transistor transistor sizes aresizes are required. required. Increased Increased gain, improved gain, improved signal- signal-to-noise ratio, and decreased overall transistor resistance to-noise ratio, and decreased overall transistor resistance are all made possible byare all made possible the sim-by the simultaneous ultaneous employmentemployment of Corbino of Corbino transistors. transistors. Also, the Also, the to ability ability to parallel parallel variousvarious num- numbers of Corbino transistors in various areas of the circuit provides bers of Corbino transistors in various areas of the circuit provides designers with designers withmore more choice choice when when creating circuits with creating circuits with diverse diverse requirements requirementsand andstandards. standards. Figure Figure 55 illustrates our design illustrates our design (together (togetherwith withother otherdesigns) designs)implemented implementedon ona aPEN PEN (polyethylene (polyethylene naphthalate) naphthalate) substrate. substrate. The ThePEN PENsubstrate substrateoffers offersseveral severaladvantages, advantages,such suchas flexibility, durability, as flexibility, and and durability, chemical resistance, chemical making resistance, it suitable making for various it suitable applications for various applica-in flexible electronics. By utilizing the PEN substrate, the overall device tions in flexible electronics. By utilizing the PEN substrate, the overall device becomesbecomes lightweight and bendable, lightweight andallowing bendable, forallowing seamlessfor integration into wearable seamless integration intodevices, wearable flexible displays, devices, flexi- and other portable electronic systems. The implementation of ble displays, and other portable electronic systems. The implementation of PEN demon-PEN demonstrates the feasibility strates theof fabricating feasibility complex electronic of fabricating complex circuits electronic oncircuits flexibleon substrates, presentingpre- flexible substrates, new possibilities senting newfor the development possibilities of flexible and for the development of portable flexible and electronic portable devices. electronic devices. Figure 5. Figure 5. Implementation Implementationofof several designs several (including designs our our (including sensors) on a flexible sensors) PEN substrate on a flexible from PEN substrate SmartKem. from SmartKem. These dies These dieswere werecreated createdwith withfour four primary primary ideas ideas in mind. in mind. TheThefirstfirst design design is com- is comprised prised of a die containing all Corbino transistors with changing of a die containing all Corbino transistors with changing W/L ratios, whereas the second W/L ratios, whereas the second design has all interdigitated transistors with varying W/L design has all interdigitated transistors with varying W/L ratios. The third design uses ratios. The third design uses identical identical W/L-sized W/L-sized interdigitated interdigitated transistors. transistors. TheThe fourth fourth designdesign combines combines Corbino Corbino and and interdigitated interdigitated transistors transistors withwith comparable comparable W/L W/L ratios ratios forfor bothboth types. types. These These designs designs are are shown shown in Figure in Figure 6. 6. Corbino transistors Corbino transistors (Figure (Figure 6a) 6a) have havebeenbeenused usedin inparallel, parallel,with withvarying varyingnumbers numbersofof transistors paralleled in each section. Each Corbino transistor has a size of W =1960 transistors paralleled in each section. Each Corbino transistor has a size of W = 1960and and L = 4. The first set has four parallel Corbino transistors, the second set has eightparallel L = 4. The first set has four parallel Corbino transistors, the second set has eight parallel Corbino transistors, Corbino transistors, the the third third setset has has two twoparallel parallelCorbino Corbinotransistors, transistors,and andthe thelast lastset sethashas just one just one parallel parallel Corbino Corbino transistor. transistor. In Figure In Figure6b, 6b,the thesecond second design design incorporates incorporates interdigitated interdigitated transistors transistors of varying of varying sizes sizes to to produce produce variedvaried gain (sensitivity) gain (sensitivity) ranges ranges on a on a single single chip.chip. The first The first circuit circuit utilizes utilizes W/L W/L ratios ratios of 980,of while 980, while the second the second circuitcircuit employs employs ratiosratios of 1960, of 1960, and and the third the third circuit circuit uses ratios of 3920. The final set of interdigitated transistors uses a W/L ratio of 2940.The uses ratios of 3920. The final set of interdigitated transistors uses a W/L ratio of 2940. The interdigitated transistor interdigitated transistor design design usesuses aa variety variety ofof W/L W/Lratios ratiosacross acrossallallthe thetransistors, transistors,inin contrast totothe contrast theCorbino Corbino transistor transistor design, design, which which uses uses parallelparallel transistors. transistors. With thisWith this method, Sensors2023, Sensors 23,x6577 2023,23, FOR PEER REVIEW 10 10 ofof2222 designers method, can altercan designers thealter transistors’ gain and the transistors’ linearity gain in accordance and linearity with certain in accordance circuit with certain needs, producing dependable and customized performance. circuit needs, producing dependable and customized performance. Four Figure6.6.Four Figure different different designs designs with with 16 ISFET 16 ISFET sensors sensors and and different different topologies: topologies: (a) Corbinos (a) Corbinos with varying W/L ratios, with varying W/L (b) interdigitated ratios, structures (b) interdigitated with different structures W/L ratios, with different W/L(c) interdigitated ratios, struc- (c) interdigitated tures with similar structures W/L ratios, with similar and (d)and W/L ratios, a combination of Corbinos (d) a combination and interdigitated of Corbinos structures. and interdigitated structures. OnOnthetheother otherhand, hand,ininFigure Figure6c, 6c,aadifferent differentdesign designapproach approachisisadopted adoptedusingusinginter- inter- digitatedtransistors digitated transistorswithwithaaconsistent consistentW/L W/Lratioratioofof980. 980.This Thisdesign designsimplifies simplifiesthe thecircuit circuit designprocess design processby by eliminating eliminating the complexity complexity of ofvarying varyingtransistor transistorsizes. sizes.ByByusing usingmatching match- transistor ing transistorsizes, a more sizes, a moreuniform uniformperformance performance across the circuit across is achieved. the circuit The The is achieved. redundancy redun- offeredoffered dancy by interdigitated transistors by interdigitated with thewith transistors sametheW/Lsameratio W/Lbecomes advantageous, ratio becomes advanta-as it enhances geous, as itcircuit reliability. enhances In the event circuit reliability. Inofthea event transistor failure, having of a transistor failure, identical-sized having identical- tran- sistors sized allows for transistors backup allows functionality, for backup which iswhich functionality, particularly criticalcritical is particularly in applications where in applications where a defective transistor can lead to severe consequences. However, it is importantnote a defective transistor can lead to severe consequences. However, it is important to to that that note this this design strategy design maymay strategy limitlimit the flexibility to customize the flexibility the transistors’ to customize performance the transistors’ perfor- properties. mance Therefore, properties. a thorough Therefore, optimization a thorough of the circuit optimization of the characteristics is required circuit characteristics is re-to strike to quired thestrike rightthe balance betweenbetween right balance benefitsbenefits and drawbacks, as previously and drawbacks, discussed. as previously discussed. Theadvantages The advantagesof of Corbino Corbino and and interdigitated interdigitated transistors transistorsare arecombined combined(Figure(Figure6d) 6d)in the interdigitated/Corbino architecture. Corbino transistors can be in the interdigitated/Corbino architecture. Corbino transistors can be chosen in this archi- chosen in this architec- ture from tecture from a group a group of of interdigitated interdigitated transistors transistorsusing MUXs. using MUXs. ThisThisprovides providesa compromise a compro- between the advantages of both types of transistors and mise between the advantages of both types of transistors and allows for greater allows for greater flexibility flexibilityin circuit design. The circuit’s flexibility to accommodate varied in circuit design. The circuit’s flexibility to accommodate varied requirements and requirements and standards stand- is further improved using interdigitated transistors with a variety ards is further improved using interdigitated transistors with a variety of W/L ratios of W/L ratios andandthe ability to parallel varying numbers of Corbino transistors in various the ability to parallel varying numbers of Corbino transistors in various regions of the regions of the cir- cuit. The circuit. The use of of use interdigitated interdigitated transistors transistors with the the with same W/LW/L same ratioratio alsoalso addsadds redundancy, redun- enhancing the circuit’s overall reliability. Table 1 presents the various types and sizes dancy, enhancing the circuit’s overall reliability. Table 1 presents the various types and of W/L (width-to-length) ratios employed in this design. As is evident from the data sizes of W/L (width-to-length) ratios employed in this design. As is evident from the data presented in Table 1, the Corbino ISFETs occupy significantly larger areas compared to the presented in Table 1, the Corbino ISFETs occupy significantly larger areas compared to interdigitated ISFETs. the interdigitated ISFETs. Sensors 2023, 23, 6577 11 of 22 Sensors 2023, 23, x FOR PEER REVIEW 11 of 22 Table 1. Different types and sizes of W/L ratios in the different chips implemented. Table 1. Different types and sizes No.ofof W/L ratios in the different chips implemented. Type W/L Area (µm2 ) Chip Transistors No. of Type Corbino 1 W/L 1960/4 = 490 Area (µm 2) 445,628 Chip (a) Transistors Corbino Corbino 12 parallel 3920/4 1960/4 = 490= 980 1,108,114 445,628 (a)(a), (d) Corbino Corbino 2 parallel 4 parallel 3920/4 = 980 7840/4 = 1960 1,108,114 1,729,239 (a), (d)(a) Corbino Corbino 4 parallel 6 parallel 7840/4 = 1960= 2940 11,760/4 1,729,239 2,596,160 (a) (d) Corbino Corbino 6 parallel 8 parallel 11,760/4 = 2940 15,680/4 = 3920 2,596,160 3,432,244 (d) (a) Corbino 8 parallel 15,680/4 = 3920 3,432,244 (a) Interdigitated 1 3920/4 = 980 49,728 (b), (c) Interdigitated 1 3920/4 = 980 49,728 (b), (c) Interdigitated 1 7840/4 = 1960 93,240 (b) Interdigitated 1 7840/4 = 1960 93,240 (b) Interdigitated Interdigitated 1 1 11,760/4 = 2940 11,760/4 = 2940 135,884 135,884 (b), (d) (b), (d) Interdigitated Interdigitated 1 1 15,680/4 15,680/4 = 3920= 3920 177,240 177,240 (b) (b) Figure 7 illustrates Figure the fabricated 7 illustrates design the fabricated for different design dies,dies, for different showcasing the variations showcasing the variations and and diversity in the physical realization of the design across multiple instances. diversity in the physical realization of the design across multiple instances. (a) (b) (c) (d) Figure 7. Images Figure of parts 7. Images of of the dies parts fabricated of the by SmartKem: dies fabricated (a) all-Corbinos by SmartKem: design (b)design (a) all-Corbinos all-inter- (b) all- digitated with different W/L ratio design (c) interdigitated/Corbino design (d) all-interdigitated interdigitated with different W/L ratio design (c) interdigitated/Corbino design (d) all-interdigitated with same W/L ratio design. with same W/L ratio design. In order to simplify In order the characterization to simplify the characterizationand and test of the test ofintegrated the integratedcircuit, the design circuit, the design includes four four includes different equivalent different structures equivalent placed structures at each placed at of the of each quarters of the chip. the quarters of theAchip. straightforward 90-degree A straightforward rotation 90-degree of the of rotation die theondie the onpackaging the packagingcan provide access can provide to to access equivalent transistors and circuits because each quarter of the dies is repeated equivalent transistors and circuits because each quarter of the dies is repeated four timesfour times on each die. die. on each Rotational access Rotational to similar access transistors to similar makes transistors it possible makes to create it possible intricate to create intricate circuits that need many transistors with the same or similar properties and also provides fault-tolerance strategies related to the device failures already described. Sensors 2023, 23, 6577 12 of 22 Sensors 2023, 23, x FOR PEER REVIEW 12 of 22 circuits that need many transistors with the same or similar properties and also provides fault-tolerance strategies related to the device failures already described. 7. OTFT Characterization To evaluate To evaluate the the performance performance of of different different transistors transistors in in the the EG-ISFET EG-ISFET sensor sensor andand OTFT MUX OTFT MUX configuration, configuration, we conducted preliminary preliminary characterization characterization experiments. experiments. These experiments provided vital insights into the behavior and efficiency efficiency of each transistor by extracting its extracting itsVV thth. .The Theexperiments experiments were were conducted conducted in tightly in tightly controlled controlled environments environments with with fixed fixed bias, humidity, bias, humidity, and temperature and temperature conditions. conditions. Based on SmartKem technology, we we were able to increase the mobility of OTFTs by applying the dual-bias dual-bias approach approach onon aa dual dual gate. gate. Using this this technique, technique, we we obtained obtained an an increase in average OTFT mobility from 0.02 cm 2 V2−1 s−1−1−1[113] to 1.949 cm2 V −1−1s−−11 with a increase in average OTFT mobility from 0.02 cm V s [113] to 1.949 cm V s 2 variability variability of of 18%. 18%. Figure 8 shows the mobility measurement measurement for for several several transistors transistors of of the the same same run. run. The mobility value utilized in this test was computed based on the calculations calculations provided provided byby Brotherton Brotherton [114]. [114]. Figure 8. Mobility test results of dual-gate transistors on 12 distinct substrates. Figure 8. Mobility test results of dual-gate transistors on 12 distinct substrates. preliminary tests These preliminary tests uncovered uncovered crucialcrucial information information about about thethe functionality functionality andand behavior of of each each transistor. transistor. During During this this test, test, the the voltage voltageofofVVdd dd was maintained at a fixed fixed value of − value −55V. V.The TheVVbgbgand andVVtgtgofofthe theOTFTs OTFTswere weresystematically systematicallyvaried varied toto extract extractthe VthVof the th each of eachtransistor. transistor.This Thisinformation informationwas wasinstrumental instrumentalininthe thefurther further testing testing and adjustment of the of thesensor sensorstructure. structure. AsAsthethe back-gate back-gate voltage voltage decreases, decreases, the threshold the threshold voltagevoltage in- increases. This behavior creases. is evidentisinevident This behavior the data in presented in Table 2,inwhere the data presented Tablethe resultsthe 2, where forresults a back-gate for a voltage back-gate −38 V are of voltage provided. of −38 According V are provided. to the definition, According Vth 1nA Vth to the definition, represents the gate 1nA represents voltage the gateintercept when thewhen voltage intercept drain the current drainiscurrent equal tois1nA fortoa specific equal 1nA for channel a specificlength (L) channel and width (W). length (L) and width (W). In Figure Figure 9a, 9a, the the I-V I-V curve curve illustrates illustrates that aa drain drain current current ofof 1nA 1nA intersects intersects with with the the curve at aa gate gate voltage voltage ofof 9.5 9.5 VV when when the the back-gate back-gate voltage voltage isisset to− setto 38 V. This behavior −38 behavior is observed consistently across the other OTFT structures structures tested. tested. However, an interesting interesting observation can be made when the Vbg is increased to 0. In this case, it becomes evident that the interdigitated transistor with double the channel width (W) experiences signifi- cant stress and ultimately fails under the same voltage condition of −27 V. Sensors 2023, 23, 6577 13 of 22 Sensors 2023, 23, x FOR PEER REVIEWobservation can be made when the Vbg is increased to 0. In this case, it becomes evident 13 of 22 that the interdigitated transistor with double the channel width (W) experiences significant stress and ultimately fails under the same voltage condition of −27 V. I_Drain vs. Vtop_gate Vback_gate 1e-5 -40 1e-6 -38 -36 1e-7 -34 -32 1e-8 -30 -28 -26 1e-9 -24 -22 1e-10 -20 -18 1e-11 -16 -14 1e-12 -12 -10 1e-13 -8 -6 1e-14 -4 -2 1e-15 0 1e-16 1e-17 1e-18 -40 -30 -20 -10 0 10 Vtop_gate (a) (b) Figure 9. I–V Figure 9. I–V curves for interdigitated curves for interdigitatedOTFTsOTFTs with with (a) (a) interdigitated interdigitated withwith W/LW/L = 3920/4 = 3920/4 and and (b) Corbino with (b) Corbino W/L with W/L1960 forfor 1960 differentVVbgbg(between different (between00 VV and − −40 V). Each 40 V). Eachvalue valueofofVbg Vbgisisrepre- represented by a different color on the graph. sented by a different color on the graph. On the On theother otherhand, when hand, examining when the Corbino examining structurestructure the Corbino (Figure 9b),(Figure it demonstrates 9b), it demon- remarkable stability under different Vbg and Vtg conditions. The Corbino configuration, strates remarkable stability under different Vbg and Vtg conditions. The Corbino configu- with its distinct design and electrode arrangement, exhibits a robust performance and ration, with its distinct design and electrode arrangement, exhibits a robust performance maintains its functionality even under varying voltage biases. and maintains its functionality even under varying voltage biases. Table 2. Variation in Vth for OTFTs at Vbg = −38 V. Type W/L Vth,mean (V) Corbino 490 12.8 ± 6% Interdigitated 980 9.5 ± 5% Sensors 2023, 23, 6577 14 of 22 Table 2. Variation in Vth for OTFTs at Vbg = −38 V. Type W/L Vth,mean (V) Corbino 490 12.8 ± 6% Interdigitated 980 9.5 ± 5% Interdigitated 1960 9.6 ± 5% Interdigitated 2940 9.7 ± 5% Interdigitated 3920 9.8 ± 5% Interdigitated (MUX) 9800 9.9 ± 5% Once we obtained the Vth values for each transistor in our EG-ISFET sensor and OTFT MUX configuration, we were able to determine the optimal effective voltages. To enhance the gain and precision of the sensor, we selected the most effective voltages for each transistor. Our careful selection of voltages ensured that the sensor could detect even the smallest changes in its environment. To ensure the sensor’s optimal performance in a variety of real-world applications, we employed these adjusted voltages in additional testing and calibration of the sensor. The characterization of SmartKem transistors in OTFTs has provided valuable insights into their operational range, spanning from −5 V to +5 V, as shown in Table 2. By applying Vbg =−38 V to the of the MUXs, the top-gate voltage of −10 V and +8 V can be effectively utilized to control the switching of the MUXs for the ISFETs. 8. Circuit Tests 8.1. Testing Set-Up To test the functionality of the MUX and EG-ISFET sensors, we used Analog Discovery 2 [115] and a standard power supply unit. We set up the measurement system such that VDD , VSS , and VBG were fixed. Using the measurement system, we swept the voltage of the top gate of the EG-ISFET sensor and measured the corresponding output current, recording the values at each step of the sweep. We repeated the test for each sensor connected to the MUX, ensuring that all connections were maintained throughout the testing process. The tests were conducted under UV-light conditions, as it has enhanced the performance of OTFTs. 8.2. Test Results The sensor circuit functionality test was designed to verify the functionality of the EG-ISFET sensor and analog MUX. This involved ensuring that the MUX was correctly controlling the flow of signals coming from the different OTFT sensors and the output, and that the transfer function between each the OTFT MUX and the output current (voltage measured on a resistor load) was accurate. 8.2.1. Multiplexing Function MUX OTFTs have been designed such that their W/L is much larger than that of the ISFET, to maximize sensitivity. Regarding our designs, all of them have the same-size W/L = 39,200/4 (all dimensions are in µm). In order to test the multiplexing function, we set the voltages in the electrical nodes of Figure 4 according to Table 3. For testing purposes, we use a 1 MΩ resistor at the output to convert current to voltage. Figure 10 illustrates the application of several voltages to the top gate of the MUXs (equivalent to a switch selector), with each color representing a different voltage. The results show that the input signal (−5 V to +5 V ramp signal) applied to the EG-ISFET electrode goes through the MUX when its control voltage is −10 V (signifying an on state), giving the maximum output range (bottom blue curve). On the other hand, when the MUX voltage is +8 V (signaling an off state), it gives the minimum (0 ± 0.01 V) output range (top Sensors 2023, 23, 6577 15 of 22 green curve), and therefore the MUX blocks the input signal and prevents it from getting to the output. In Figure 10, the input ramp signals (not shown) applied for the different MUX control voltages are not aligned, to better show the output signal behavior. Table 3. Input values ranges for multiplexer test (dynamic). I/O Dir. Unit Value Sensors 2023, 23, x FOR PEER REVIEW VDD Input Voltage −5 15 of 22 VBG,mux Input Voltage −38 VBG,sensor Input Voltage −38 voltage is +8 V (signaling an off state), VTG,mux Input it gives the minimum Voltage(0 ± 0.01 V) output range (top −10~+8 green curve), and therefore the MUX blocks the input signal and prevents it from getting VTG,sensor Input Voltage −5~+5 to the output. In Figure 10, the input ramp signals (not shown) applied for the different Source MUX control Output to better show the voltages are not aligned, Current Measure output signal behavior. Output vs. Time (s) TG-MUX 0 -10 -9 -8 -7 -6 -5 -4 -1 -3 -2 -1 0 1 2 3 4 -2 5 6 7 8 -3 -0.0006 -0.0004 -0.0002 0 0.0002 0.0004 0.0006 Time (s) (a) (b) Figure Figure10. 10.Signal Signalpropagation propagation from from the EG-ISFET gate to to the the output outputof ofthe theMUX MUXforfordifferent differenttop-gate top- gate voltages voltages and and (a)interdigitated (a) an an interdigitated andand (b) a(b) a Corbino Corbino topology topology (W/L (W/L = 3920/4for = 3920/4 forboth). both). Corbino transistors show faster reactions from input to output; they are visible as less-curved responses. This is due to the larger output capacitance per width of interdigi- tated topologies. 8.2.2. Global Sensing Function In this section, we test the global transfer function from a voltage applied to the input Sensors 2023, 23, 6577 16 of 22 Corbino transistors show faster reactions from input to output; they are visible as less-curved responses. This is due to the larger output capacitance per width of interdigi- tated topologies. 8.2.2. Global Sensing Function In this section, we test the global transfer function from a voltage applied to the input of the ISFET (ideally coming from the external electrode) to the output current obtained Sensors 2023, 23, x FOR PEER REVIEW after the analog MUX. 16 of 22 For testing purposes, we use a 1 MΩ resistor at the output to convert the current to a voltage, to later obtain transconductance values for each of the circuit designs. The results of ofthese thesetests testsare arepresented presentedin inFigure Figure11. 11.Each Eachbar barwithin within Figure Figure1111represents representsthe theoutput output current obtained when the input signal is a ramp ranging from − 5 V current obtained when the input signal is a ramp ranging from −5 V to 5 V.to 5 V. Figure 11. Figure 11. Global Global transfer transferfunction functionresults resultsshowing showingthe relationship the between relationship thethe between input voltage input ap- voltage plied to the ISFET and the corresponding output current after passing through the analog MUX. applied to the ISFET and the corresponding output current after passing through the analog MUX. 8.2.3. Transconductance 8.2.3. TransconductanceResults Results Thetransconductance The transconductancefindings findingsfrom from thethe experimental experimental measurements measurements are are shownshown in in the the Table Table 4. 4. Brotherton [114] suggested calculating the transconductance (gm) based on the fol- Table lowing4. Transconductance formula: comparison between different designs under VTG, MUX = −10. No. 𝑑𝐼 Design Topology µ 𝑊𝐶 𝑉 gm 𝑔 ≡ 1 𝑑𝑉= 1960/4)𝐿 1 Corbino (W/L 1.18 × 10−7 ± 5% By considering 2 a capacitance value 2 Corbinos (W/L of =C3920/4) i = 6 nf/cm2, we can 1.21 × 10−7the calculate transcon- ± 5% ductance for 3 different transistor designs. 4 Corbinos (W/L By=calculating 7840/4) the transconductance, 1.44 × 10−7 ± we 5% can as- sess the effectiveness of the transistor in controlling the flow of current through the channel. 4 6 Corbinos (W/L = 11,760/4) 1.35 × 10−7 ± 5% Table 4 shows the summary of these findings and offers a thorough comparison of 6 the improvements made by Interdigitated (W/Lconfigurations various design = 3920/4) the × during1.49 10−test. final 7 ± 5% The table makes it simple 7 to evaluate each design’s performance Interdigitated (W/L = 7840/4) and makes it − easier7 1.47 × 10 ± 5%to determine which design 8 is the most profitable. It is possible Interdigitated (W/L = 11,760/4) to learn a lot about the amplification 1.09 × 10−7 ± 5% potential and effectiveness of the various configurations by analyzing the gains made by each design. For assessing and choosing the best design for a given application, the gain Brotherton values achieved[114] suggested are crucial calculating information. the transconductance Measurements have been(gtaken m ) based on thedifferent on eight follow- ing formula: chips fabricated in the same run. dId µn WCi VD gm ≡ = Table 4. Transconductance comparison betweendVG different L designs under VTG, MUX = −10. No. Design Topology gm 1 1 Corbino (W/L = 1960/4) 1.18 × 10−7 ± 5% 2 2 Corbinos (W/L = 3920/4) 1.21 × 10−7 ± 5% Sensors 2023, 23, 6577 17 of 22 By considering a capacitance value of Ci = 6 nf/cm2 , we can calculate the transconduc- tance for different transistor designs. By calculating the transconductance, we can assess the effectiveness of the transistor in controlling the flow of current through the channel. Table 4 shows the summary of these findings and offers a thorough comparison of the improvements made by various design configurations during the final test. The table makes it simple to evaluate each design’s performance and makes it easier to determine which design is the most profitable. It is possible to learn a lot about the amplification potential and effectiveness of the various configurations by analyzing the gains made by each design. For assessing and choosing the best design for a given application, the gain values achieved are crucial information. Measurements have been taken on eight different chips fabricated in the same run. Measurements for both the eight Corbinos (5.76 × 10−8 ± 5%) and large (W/L = 15,680/4) interdigitated (8.90 × 10−8 ± 5%) designs exhibit a decrease in the output voltage, suggesting that the input voltage needs to be lower than −5 V to achieve the maximum output range and the corresponding accurate transconductance. Table 5 offers a comparison of the performance of the present design with results from three existing OTFT ISFETs found in the literature. The table encompasses mobility, transconductance, and area. In our method, utilizing a dual-gate approach, we were able to significantly increase the mobility. Our best case for transconductance values is slightly higher than the best of those found in the literature, while the area is in the same range as the others. Table 5. Transconductance comparison between different designs under VTG, MUX = −10. Mobility Transconductance (S) Area (mm2 ) (cm2 V−1 s−1 ) Proposed Method 1.949 1.49 × 10−7 0.4 Claramunt S., et al. [116] 0.55 1.4 × 10−7 - Wu S.J., et al. [117] 0.33 0.99 × 10−8 0.5 Saini D., et al. [113] 0.02 0.3 × 10−7 0.2 9. Conclusions We have developed a novel sensor circuit structure by mixing extended ISFET sensors and multiplexers using dual-gate OTFTs, which presents a new model for implementing flexible and environment-friendly sensor chips. Multiplexing can be used to select different gains and sensitivities as well as to replace damaged devices (e.g., due to ESD failures). The ability to easily switch between ISFETs can be controlled by a simple MCU embed- ding ADC elementary analogs and digital blocks, thus improving the sensor system’s overall functionality. The OTFT fabrication process is much simpler and cheaper than that of silicon-based technologies. Due to the lack of a CMOS process in the organic domain, dual-gate OTFTs are mandatory to build multiplexers that can block the signal coming from one of the ISFETs while processing the other one. The SmartKem 2.5 micron process allows for fabricating them. The use of digital patterning even removes the requirement of fabricating masks, what usually increases NRE costs. Still, some work must be conducted to obtain validated electrical models, to allow for better analysis and simulation. It is worth mentioning that OTFT ISFETs offer a recyclable advantage over conven- tional ISFETs, making them an environmentally friendly option for sensing applications. The use of organic materials for OTFT ISFETs in a low-temperature process enables the development of devices that can be easily recycled and disposed of in an eco-friendly man- ner. Unlike conventional ISFETs, which often contain rigid and non-recyclable materials like silicon substrates, OTFT ISFETs can be fabricated on flexible and recyclable substrates such as eco-friendly plastic or paper. This reduces the environmental impact associated Sensors 2023, 23, 6577 18 of 22 with electronic waste and promotes a more sustainable approach to device manufacturing and deployment. Our designs contain different Corbino and interdigitated structures, for which we have evaluated the output voltage, current, area, and transconductance under various input conditions and dimensions. The interdigitated transistors with a W/L ratio of 3920/4 stand out as the most advantageous in terms of transconductance among the tested configurations and have a 23% better performance than the Corbino topology with the same dimensions. Some further research could be conducted to tune the technology parameters (out of our capabilities), to optimize the operational ranges for voltage supply and the bias of the entire system. Author Contributions: Conceptualization, A.R. and J.C.; Methodology, A.R. and J.C.; Software, A.R.; Validation, A.R.; Investigation, A.R. and J.C.; Resources, A.R. and J.C.; Data curation, A.R.; Writing—original draft, A.R.; Writing—review & editing, A.R. and J.C.; Supervision, J.C.; Funding acquisition, J.C. All authors have read and agreed to the published version of the manuscript. Funding: This research has been partly funded by Catalan Government Research groups 2021SGR01623. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. Data Availability Statement: Data sharing not applicable. Acknowledgments: I would want to thank Simon Ogier for all their help and support throughout several years of dialog. I would also thank Alejandro Carreras, and Dan Sharkey from SmartKem Ltd. for helping with processing and testing my design. I want to express my gratitude to August Arnal, and Miquel Moras from FlexiiC and E. Ramon, L. Teres from Institute of Microelectronics of Barcelona, IMB-CNM (CSIC) for providing the tools and resources needed for this research to be carried out successfully. Conflicts of Interest: The authors declare no conflict of interest. References 1. Tixier-Mita, A.; Ihida, S.; Ségard, B.-D.; Cathcart, G.; Takahashi, T.; Fujita, H.; Toshiyoshi, H. Review on thin-film transistor technology, its applications, and possible new applications to biological cells. Jpn. J. Appl. Phys. 2016, 55, 04EA08. [CrossRef] 2. Kumar, A.; Goyal, A.K.; Gupta, N. Review—Thin-Film Transistors (TFTs) for Highly Sensitive Biosensing Applications: A Review. ECS J. Solid State Sci. Technol. 2020, 9, 115022. [CrossRef] 3. Weimer, P.K. The TFT A New Thin-Film Transistor. Proc. IRE 1962, 50, 1462–1469. [CrossRef] 4. Lechner, B.; Marlowe, F.; Nester, E.; Tults, J. Liquid crystal matrix displays. In Proceedings of the 1969 IEEE International Solid-State Circuits Conference, Philadelphia, PA, USA, 19–21 February 1969. [CrossRef] 5. Le Comber, P.; Spear, W.; Ghaith, A. Amorphous-silicon field-effect device and possible application. Electron. Lett. 1979, 15, 179–181. [CrossRef] 6. Tiedje, T.; Abeles, B.; Morel, D.L.; Moustakas, T.D.; Wronski, C.R. Electron drift mobility in hydrogenated a-Si. Appl. Phys. Lett. 1980, 36, 695–697. [CrossRef] 7. Depp, S.; Juliana, A.; Huth, B. Polysilicon FET devices for large area input/output applications. In Proceedings of the 1980 International Electron Devices Meeting, Washington, DC, USA, 8–10 December 1980. [CrossRef] 8. Gao, X.; Lin, L.; Liu, Y.; Huang, X. LTPS TFT Process on Polyimide Substrate for Flexible AMOLED. J. Disp. Technol. 2015, 11, 666–669. [CrossRef] 9. Serikawa, T.; Shirai, S.; Okamoto, A.; Suyama, S. Low temperature fabrication of high mobility poly-Si TFTs for large area LCDs. IEEE Trans. Electron Devices 1989, 36, 1929–1933. [CrossRef] 10. Miyata, Y.; Furuta, M.; Yoshioka, T.Y.T.; Kawamura, T.K.T. Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display. Jpn. J. Appl. Phys. 1992, 31, 4559. [CrossRef] 11. Biggs, J.; Myers, J.; Kufel, J.; Ozer, E.; Craske, S.; Sou, A.; Ramsdale, C.; Williamson, K.; Price, R.; White, S. A natively flexible 32-bit Arm microprocessor. Nature 2021, 595, 532–536. [CrossRef] 12. Ebisawa, F.; Kurokawa, T.; Nara, S. Electrical properties of polyacetylene/polysiloxane interface. J. Appl. Phys. 1983, 54, 3255–3259. [CrossRef] 13. Drury, C.J.; Mutsaers, C.M.J.; Hart, C.M.; Matters, M.; de Leeuw, D.M. Low-cost all-polymer integrated circuits. Appl. Phys. Lett. 1998, 73, 108–110. [CrossRef] 14. Guo, X.; Xu, Y.; Ogier, S.; Ng, T.N.; Caironi, M.; Perinot, A.; Li, L.; Zhao, J.; Tang, W.; Sporea, R.A.; et al. Current Status and Opportunities of Organic Thin-Film Transistor Technologies. IEEE Trans. Electron Devices 2017, 64, 1906–1921. [CrossRef] Sensors 2023, 23, 6577 19 of 22 15. Jenkins, E. High-performance apparel for outdoor pursuits. In High-Performance Apparel: Materials, Development, and Applications; Elsevier: Amsterdam, The Netherlands, 2017; pp. 421–449. 16. Koezuka, H.; Tsumura, A.; Ando, T. Field-effect transistor with polythiophene thin film. Synth. Met. 1987, 18, 699–704. [CrossRef] 17. Park, C.B.; Kim, K.M.; Lee, J.E.; Na, H.; Yoo, S.S.; Yang, M.S. Flexible electrophoretic display driven by solution-processed organic TFT with highly stable bending feature. Org. Electron. 2014, 15, 3538–3545. [CrossRef] 18. Chen, C.-M.; Anastasova, S.; Zhang, K.; Gil Rosa, B.; Lo, B.P.L.; Assender, H.E.; Yang, G.-Z. Towards Wearable and Flexible Sensors and Circuits Integration for Stress Monitoring. IEEE J. Biomed. Heal. Inform. 2019, 24, 2208–2215. [CrossRef] [PubMed] 19. Myny, K.; Steudel, S.; Smout, S.; Vicca, P.; Furthner, F.; van der Putten, B.; Tripathi, A.; Gelinck, G.; Genoe, J.; Dehaene, W.; et al. Organic RFID transponder chip with data rate compatible with electronic product coding. Org. Electron. 2010, 11, 1176–1179. [CrossRef] 20. Fiore, V.; Battiato, P.; Abdinia, S.; Jacobs, S.; Chartier, I.; Coppard, R.; Klink, G.; Cantatore, E.; Ragonese, E.; Palmisano, G. An Integrated 13.56-MHz RFID Tag in a Printed Organic Complementary TFT Technology on Flexible Substrate. IEEE Trans. Circuits Syst. I Regul. Pap. 2015, 62, 1668–1677. [CrossRef] 21. Shiwaku, R.; Matsui, H.; Nagamine, K.; Uematsu, M.; Mano, T.; Maruyama, Y.; Nomura, A.; Tsuchiya, K.; Hayasaka, K.; Takeda, Y.; et al. A Printed Organic Amplification System for Wearable Potentiometric Electrochemical Sensors. Sci. Rep. 2018, 8, 3922. [CrossRef] 22. Minemawari, H.; Yamada, T.; Matsui, H.; Tsutsumi, J.; Haas, S.; Chiba, R.; Kumai, R.; Hasegawa, T. Inkjet printing of single-crystal films. Nature 2011, 475, 364–367. [CrossRef] 23. Venkateshvaran, D.; Nikolka, M.; Sadhanala, A.; Lemaur, V.; Zelazny, M.; Kepa, M.; Hurhangee, M.; Kronemeijer, A.J.; Pecunia, V.; Nasrallah, I.; et al. Approaching disorder-free transport in high-mobility conjugated polymers. Nature 2014, 515, 384–388. [CrossRef] 24. Sirringhaus, H. 25th Anniversary Article: Organic Field-Effect Transistors: The Path Beyond Amorphous Silicon. Adv. Mater. 2014, 26, 1319–1335. [CrossRef] 25. Shao, Y.; Xiao, Z.; Bi, C.; Yuan, Y.; Huang, J. Origin and elimination of photocurrent hysteresis by fullerene passivation in CH3NH3PbI3 planar heterojunction solar cells. Nat. Commun. 2014, 5, 5784. [CrossRef] 26. Fan, H.; Zou, S.; Gao, J.; Chen, R.; Ma, Q.; Ma, W.; Zhang, H.; Chen, G.; Huo, X.; Liu, Z.; et al. High-mobility organic single- crystalline transistors with anisotropic transport based on high symmetrical “H”-shaped heteroarene derivatives. J. Mater. Chem. C 2020, 8, 11477–11484. [CrossRef] 27. Paterson, A.F.; Singh, S.; Fallon, K.J.; Hodsden, T.; Han, Y.; Schroeder, B.C.; Bronstein, H.; Heeney, M.; McCulloch, I.; Anthopoulos, T.D. Recent Progress in High-Mobility Organic Transistors: A Reality Check. Adv. Mater. 2018, 30, e1801079. [CrossRef] 28. Kim, N.S.; Austin, T.; Blaauw, D.; Mudge, T.; Flautner, K.; Hu, J.S.; Irwin, M.; Kandemir, M.; Narayanan, V. Leakage current: Moore’s law meets static power. Computer 2003, 36, 68–75. [CrossRef] 29. Steudel, S.; Myny, K.; De Vusser, S.; Genoe, J.; Heremans, P. Patterning of organic thin film transistors by oxygen plasma etch. Appl. Phys. Lett. 2006, 89, 183503. [CrossRef] 30. Tang, W.; Zhao, J.; Feng, L.; Yu, P.; Zhang, W.; Guo, X. Top-Gate Dry-Etching Patterned Polymer Thin-Film Transistors With a Protective Layer on Top of the Channel. IEEE Electron Device Lett. 2014, 36, 59–61. [CrossRef] 31. Borchert, J.W.; Zschieschang, U.; Letzkus, F.; Giorgio, M.; Weitz, R.T.; Caironi, M.; Burghartz, J.N.; Ludwigs, S.; Klauk, H. Flexible low-voltage high-frequency organic thin-film transistors. Sci. Adv. 2020, 6, eaaz5156. [CrossRef] [PubMed] 32. Chang, T.K.; Lin, C.W.; Chang, S. LTPO TFT technology for amoleds. Dig. Tech. Pap. 2019, 50, 545–548. [CrossRef] 33. Sameshima, T.; Sekiya, M.; Usui, S. XeCl Excimer Laser Annealing used in the Fabrication of Poly-Si TFTs. IEEE Electron Device Lett. 1986, 7, 276–278. [CrossRef] 34. Klauk, H.; Halik, M.; Zschieschang, U.; Schmid, G.; Radlik, W.; Weber, W. High-mobility polymer gate dielectric pentacene thin film transistors. J. Appl. Phys. 2002, 92, 5259–5263. [CrossRef] 35. Forrest, S.R. The path to ubiquitous and low-cost organic electronic appliances on plastic. Nature 2004, 428, 911–918. [CrossRef] [PubMed] 36. Zhang, Y.; Li, D.; Jiang, C. Influence of grain size at first monolayer on bias-stress effect in pentacene-based thin film transistors. Appl. Phys. Lett. 2013, 103, 213304. [CrossRef] 37. Huang, S.-P.; Chen, H.-C.; Chen, P.-H.; Zheng, Y.-Z.; Chu, A.-K.; Shih, Y.-S.; Wang, Y.-X.; Wu, C.-C.; Chen, Y.-A.; Sun, P.-J.; et al. Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors. IEEE Trans. Electron Devices 2020, 67, 3163–3166. [CrossRef] 38. Zheng, Y.-Z.; Huang, S.-P.; Chen, P.-H.; Chang, T.-C.; Tsai, T.-M.; Chu, A.-K.; Hung, Y.-H.; Shih, Y.-S.; Wang, Y.-X.; Wu, C.-C.; et al. Enhancement of Mechanical Bending Stress Endurance Using an Organic Trench Structure in Foldable Polycrystalline Silicon TFTs. IEEE Electron Device Lett. 2020, 41, 721–724. [CrossRef] 39. Lee, J.-H.; Kim, D.-H.; Yang, D.-J.; Hong, S.-Y.; Yoon, K.-S.; Hong, P.-S.; Jeong, C.-O.; Park, H.-S.; Kim, S.Y.; Lim, S.K.; et al. 42.2: World’s Largest (15-inch) XGA AMLCD Panel Using IGZO Oxide TFT. Dig. Tech. Pap. 2008, 39, 625–628. [CrossRef] 40. Kim, M.; Ryu, S.U.; Park, S.A.; Choi, K.; Kim, T.; Chung, D.; Park, T. Donor–Acceptor-Conjugated Polymer for High-Performance Organic Field-Effect Transistors: A Progress Report. Adv. Funct. Mater. 2020, 30, 1904545. [CrossRef] 41. Fratini, S.; Nikolka, M.; Salleo, A.; Schweicher, G.; Sirringhaus, H. Charge transport in high-mobility conjugated polymers and molecular semiconductors. Nat. Mater. 2020, 19, 491–502. [CrossRef] Sensors 2023, 23, 6577 20 of 22 42. Phan, H.; Wang, M.; Bazan, G.C.; Nguyen, T.-Q. Electrical Instability Induced by Electron Trapping in Low-Bandgap Donor- Acceptor Polymer Field-Effect Transistors. Adv. Mater. 2015, 27, 7004–7009. [CrossRef] 43. Wu, X.; Jia, R.; Jie, J.; Zhang, M.; Pan, J.; Zhang, X.; Zhang, X. Air Effect on the Ideality of p-Type Organic Field-Effect Transistors: A Double-Edged Sword. Adv. Funct. Mater. 2019, 29, 1906653. [CrossRef] 44. Yang, Z.; Guo, C.; Shi, C.; Wang, D.K.; Zhang, T.; Zhu, Q.; Lu, Z.H. Improving Bias-Stress Stability of p-Type Organic Field-Effect Tran-sistors by Constructing an Electron Injection Barrier at the Drain Electrode/Semiconductor Interfaces. ACS Appl. Mater. Interfaces 2020, 12, 41886–41895. [CrossRef] 45. Nikolka, M.; Nasrallah, I.; Rose, B.; Ravva, M.K.; Broch, K.; Sadhanala, A.; Harkin, D.; Charmet, J.; Hurhangee, M.; Brown, A.; et al. High operational and environmental stability of high-mobility conjugated polymer field-effect transistors through the use of molecular additives. Nat. Mater. 2017, 16, 356–362. [CrossRef] [PubMed] 46. Phan, H.; Ford, M.J.; Lill, A.T.; Wang, M.; Bazan, G.C.; Nguyen, T.-Q. Improving Electrical Stability and Ideality in Organic Field-Effect Transistors by the Addition of Fullerenes: Understanding the Working Mechanism. Adv. Funct. Mater. 2017, 27, 1701358. [CrossRef] 47. Xu, Y.; Sun, H.; Shin, E.-Y.; Lin, Y.-F.; Li, W.; Noh, Y.-Y. Planar-Processed Polymer Transistors. Adv. Mater. 2016, 28, 8531–8537. [CrossRef] 48. Wu, X.; Jia, R.; Pan, J.; Wang, J.; Deng, W.; Xiao, P.; Zhang, X.; Jie, J. Improving Ideality of P-Type Organic Field-Effect Transistors via Preventing Undesired Minority Carrier Injection. Adv. Funct. Mater. 2021, 31, 2100202. [CrossRef] 49. Wang, C.; Dong, H.; Jiang, L.; Hu, W. Organic semiconductor crystals. Chem. Soc. Rev. 2018, 47, 422–500. [CrossRef] 50. Liu, C.; Jang, J.; Xu, Y.; Kim, H.-J.; Khim, D.; Park, W.-T.; Noh, Y.-Y.; Kim, J.-J. Effect of Doping Concentration on Microstructure of Conjugated Polymers and Characteristics in N-Type Polymer Field-Effect Transistors. Adv. Funct. Mater. 2014, 25, 758–767. [CrossRef] 51. Lüssem, B.; Keum, C.M.; Kasemann, D.; Naab, B.; Bao, Z.; Leo, K. Doped Organic Transistors. Chem. Reviews. Am. Chem. Soc. 2016, 116, 13714–13751. [CrossRef] 52. Bausells, J.; Carrabina, J.; Errachid, A.; Merlos, A. Ion-sensitive field-effect transistors fabricated in a commercial CMOS technology. Sens. Actuators B Chem. 1999, 57, 56–62. [CrossRef] 53. Hansen, C.L.; Skordalakest, E.; Berger, J.M.; Quake, S.R. A robust and scalable microfluidic metering method that allows protein crystal growth by free interface diffusion. Proc. Natl. Acad. Sci. USA 2002, 99, 16531–16536. [CrossRef] 54. Takayama, S.; Ostuni, E.; LeDuc, P.; Naruse, K.; Ingber, D.E.; Whitesides, G.M. Subcellular positioning of small molecules. Nature 2001, 411, 1016. [CrossRef] 55. Son, J.; Samuel, R.; Gale, B.K.; Carrell, D.T.; Hotaling, J.M. Separation of sperm cells from samples containing high concentrations of white blood cells using a spiral channel. Biomicrofluidics 2017, 11, 054106. [CrossRef] 56. Jafek, A.R.; Harbertson, S.; Brady, H.; Samuel, R.; Gale, B.K. Instrumentation for xPCR Incorporating qPCR and HRMA. Anal. Chem. 2018, 90, 7190–7196. [CrossRef] 57. Bange, A.; Halsall, H.B.; Heineman, W.R. Microfluidic immunosensor systems. Biosens. Bioelectron. 2005, 20, 2488–2503. [CrossRef] 58. Guo, M.T.; Rotem, A.; Heyman, J.A.; Weitz, D.A. Droplet microfluidics for high-throughput biological assays. Lab Chip 2012, 12, 2146–2155. [CrossRef] 59. Safdar, M.; Jänis, J.; Sánchez, S. Microfluidic fuel cells for energy generation. Lab Chip 2016, 16, 2754–2758. [CrossRef] [PubMed] 60. Xia, Y.; Whitesides, G.M. Soft lithography. Annu. Rev. Mater. Sci. 1998, 28, 153–184. [CrossRef] 61. McDonald, J.C.; Duffy, D.C.; Anderson, J.R.; Chiu, D.T.; Wu, H.; Schueller, O.J.; Whitesides, G.M. Fabrication of microfluidic systems in poly(dimethylsiloxane). Electrophoresis 2000, 21, 27–40. [CrossRef] 62. Qin, D.; Xia, Y.; Whitesides, G.M. Soft lithography for micro- and nanoscale patterning. Nat. Protoc. 2010, 5, 491–502. [CrossRef] 63. Faustino, V.; Catarino, S.O.; Lima, R.; Minas, G. Biomedical microfluidic devices by using low-cost fabrication techniques: A review. J. Biomech. 2016, 49, 2280–2292. [CrossRef] [PubMed] 64. Telting-Diaz, M.; Bakker, E. Mass-Produced Ionophore-Based Fluorescent Microspheres for Trace Level Determination of Lead Ions. Anal. Chem. 2002, 74, 5251–5256. [CrossRef] [PubMed] 65. Wang, X.; Zhang, X. Electrochemical co-reduction synthesis of graphene/nano-gold composites and its application to electro- chemical glucose biosensor. Electrochim Acta. 2013, 112, 774–782. [CrossRef] 66. Privett, B.J.; Shin, J.H.; Schoenfisch, M.H. Electrochemical sensors. Anal Chem. 2010, 82, 4723–4741. [CrossRef] [PubMed] 67. Chen, C.; Kotyk, J.F.K.; Sheehan, S.W. Progress toward Commercial Application of Electrochemical Carbon Dioxide Reduction. Chem 2018, 4, 2571–2586. [CrossRef] 68. Wang, Y.; Xu, H.; Zhang, J.; Li, G. Electrochemical Sensors for Clinic Analysis. Sensors 2008, 8, 2043–2081. [CrossRef] [PubMed] 69. Nurul Islam, M.; Mazhari, B. Organic thin film transistors with asymmetrically placed source and drain contact. Org. Electron. 2013, 14, 862–867. [CrossRef] 70. Jeon, J.H.; Cho, W.J. High-performance extended-gate ion-sensitive field-effect transistors with multi-gate structure for trans- parent, flexible, and wearable biosensors. Sci. Technol. Adv. Mater. 2020, 21, 371–378. [CrossRef] 71. Zeng, R.; Zhang, J.; Sun, C.; Xu, M.; Zhang, S.-L.; Wu, D. A reference-less semiconductor ion sensor. Sens. Actuators B Chem. 2018, 254, 102–109. [CrossRef] 72. Vonau, W.; Gerlach, F.; Herrmann, S. Conception of a new technique in cell cultivation using a lab-on-chip aided miniaturised device with calibratable electrochemical sensors. Microchim. Acta 2010, 171, 451–456. [CrossRef] Sensors 2023, 23, 6577 21 of 22 73. Parizi, K.B.; Xu, X.; Pal, A.; Hu, X.; Wong, H.S.P. ISFET pH Sensitivity: Counter-Ions Play a Key Role. Sci. Rep. 2017, 7, 41305. [CrossRef] 74. Bouftas, M. A Systematic Review on the Feasibility of Salivary Biomarkers for Alzheimer’s Disease. J. Prev. Alzheimer’s Dis. 2021, 8, 84–91. [CrossRef] 75. Lau, H.-C.; Lee, I.-K.; Ko, P.-W.; Lee, H.-W.; Huh, J.-S.; Cho, W.-J.; Lim, J.-O. Non-Invasive Screening for Alzheimer’s Disease by Sensing Salivary Sugar Using Drosophila Cells Expressing Gustatory Receptor (Gr5a) Immobilized on an Extended Gate Ion-Sensitive Field-Effect Transistor (EG-ISFET) Biosensor. PLoS ONE 2015, 10, e0117810. [CrossRef] 76. McKinley, B.A. ISFET and Fiber Optic Sensor Technologies: In Vivo Experience for Critical Care Monitoring. Chem. Rev. 2008, 108, 826–844. [CrossRef] 77. Baghini, M.S.; Vilouras, A.; Douthwaite, M.; Georgiou, P.; Dahiya, R. Ultra-thin ISFET-based sensing systems. Electrochem. Sci. Adv. 2022, 2, e2100202. 78. Pirson, T.; Delhaye, T.; Pip, A.; Le Brun, G.; Raskin, J.-P.; Bol, D. The Environmental Footprint of IC Production: Meta-Analysis and Historical Trends. In Proceedings of the ESSDERC 2022-IEEE 52nd European Solid-State Device Research Conference (ESSDERC), Milan, Italy, 19–22 September 2022; pp. 352–355. [CrossRef] 79. Ogier, S.; Sharkey, D.; Carreras, A.; Tsai, S. 69-3: Opportunities for High-Performance Display Manufacturing Enabled by OTFTs Using an 80*C Maximum Process Temperature. SID Symp. Dig. Tech. Pap. 2022, 53, 929–932. [CrossRef] 80. Zheng, Y.-Z.; Chen, Y.-A.; Chen, P.-H.; Chang, T.-C.; Hung, Y.-H.; Zhou, K.-J.; Tu, Y.-F.; Wang, Y.-X.; Chen, J.-J.; Wu, C.-C.; et al. Physical Mechanism of the Mechanical Bending of High-Performance Organic TFTs and the Effect of Atmospheric Factors. ACS Appl. Electron. Mater. 2022, 4, 3000–3009. [CrossRef] 81. Zschieschang, U.; Klauk, H.; Borchert, J.W. High-Resolution Lithography for High-Frequency Organic Thin-Film Transistors. Adv. Mater. Technol. 2023, 8, 2201888. [CrossRef] 82. Cavallari, M.R.; Pastrana, L.M.; Sosa, C.D.F.; Marquina, A.M.R.; Izquierdo, J.E.E.; Fonseca, F.J.; de Amorim, C.A.; Paterno, L.G.; Kymissis, I. Organic Thin-Film Transistors as Gas Sensors: A Review. Materials 2020, 14, 3. [CrossRef] [PubMed] 83. Bilgaiyan, A.; Cho, S.-I.; Abiko, M.; Watanabe, K.; Mizukami, M. Flexible, high mobility short-channel organic thin film transistors and logic circuits based on 4H–21DNTT. Sci. Rep. 2021, 11, 11710. [CrossRef] [PubMed] 84. Gupta, S.; Singh, M.K. Key aspects affecting the performances of high-K dielectrics based single-gate and dual-gate OTFTs. Mater. Today Proc. 2021, 50, 231–237. [CrossRef] 85. Kumar, B.; Kaushik, B.K.; Negi, Y.S.; Goswami, V. Single and dual gate OTFT based robust organic digital design. Microelectron. Reliab. 2014, 54, 100–109. [CrossRef] 86. Ha, T.-J.; Kiriya, D.; Chen, K.; Javey, A. Highly Stable Hysteresis-Free Carbon Nanotube Thin-Film Transistors by Fluorocarbon Polymer Encapsulation. ACS Appl. Mater. Interfaces 2014, 6, 8441–8446. [CrossRef] 87. Dou, W.; Tan, Y. Dual-gate low-voltage transparent electric-double-layer thin-film transistors with a top gate for threshold voltage modulation. RSC Adv. 2020, 10, 8093–8096. [CrossRef] [PubMed] 88. Duvvury, C.; Amerasekera, A. ESD: A pervasive reliability concern for IC technologies. Proc. IEEE 1993, 81, 690–702. [CrossRef] 89. Kleinman, D.A.; Schawlow, A.L. Corbino disk. J. Appl. Phys. 1960, 31, 2176–2187. [CrossRef] 90. Guzenko, V.A.; Akabori, M.; Schäpers, T.; Cabañas, S.; Sato, T.; Suzuki, T.; Yamada, S. Weak antilocalization measurements on a 2-dimensional electron gas in an InGaSb/InAlSb heterostructure. Phys. Status Solidi 2006, 3, 4227–4230. [CrossRef] 91. Klauk, H.; Gundlach, D.; Nichols, J.; Jackson, T. Pentacene organic thin-film transistors for circuit and display applications. IEEE Trans. Electron. Devices 1999, 46, 1258–1263. [CrossRef] 92. Arnal, A.; Martínez-Domingo, C.; Ogier, S.; Terés, L.; Ramon, E. Monotype Organic Dual Threshold Voltage Using Different OTFT Geometries. Crystals 2019, 9, 333. [CrossRef] 93. Byun, Y.H.; Den Boer, W.; Yang, M.; Gu, T. An amorphous silicon TFT with annu-lar-shaped channel and reduced gate-source capacitance. IEEE Trans. Electron. Devices 1996, 43, 839–841. [CrossRef] 94. Munteanu, D.; Cristoloveanu, S.; Hovel, H. Circular pseudo-metal oxide semiconductor field effect transistor in sili-con-on- insulator analytical model, simulation, and measurements. Electrochem. Solid-State Lett. 1999, 2, 242–243. [CrossRef] 95. Zhao, C.; Fung, T.C.; Kanicki, J. Half-Corbino short-channel amorphous In–Ga–Zn–O thin-film transistors with a-SiOx or a-SiOx/a-SiNx passivation layers. Solid State Electron. 2016, 120, 25–31. [CrossRef] 96. Kong, J.; Liu, C.; Li, X.; Ou, H.; She, J.; Deng, S.; Chen, J. Characteristics of Offset Corbino Thin Film Transistor: A Physical Model. Electronics 2023, 12, 2195. [CrossRef] 97. Mativenga, M.; Geng, D.; Um, J.K.; Mruthyunjaya, R.K.; Heiler, G.N.; Tredwell, T.J.; Jang, J. 49.2: Corbino TFTs for Large-Area AMOLED Displays. SID Symp. Dig. Tech. Pap. 2014, 45, 705–708. [CrossRef] 98. Das, M.B.; Josephy, R.D. High Frequency, High Power Igfet with Interdigital Electrodes and Plural Looped Gate. U.S. Patent 3,586,930, 10 March 1971. 99. Tisserant, J.-N.; Wicht, G.; Göbel, O.F.; Bocek, E.; Bona, G.-L.; Geiger, T.; Hany, R.; Mezzenga, R.; Partel, S.; Schmid, P.; et al. Growth and Alignment of Thin Film Organic Single Crystals from Dewetting Patterns. ACS Nano 2013, 7, 5506–5513. [CrossRef] [PubMed] 100. Bi, S.; He, Z.; Chen, J.; Li, D. Solution-grown small-molecule organic semiconductor with enhanced crystal alignment and areal coverage for organic thin film transistors. AIP Adv. 2015, 5, 077170. [CrossRef] Sensors 2023, 23, 6577 22 of 22 101. Fujisaki, Y.; Takahashi, D.; Nakajima, Y.; Nakata, M.; Tsuji, H.; Yamamoto, T. Alignment Control of Patterned Organic Semicon- ductor Crystals in Short-Channel Transistor Using Unidirectional Solvent Evaporation Process. IEEE Trans. Electron. Devices 2015, 62, 2306–2312. [CrossRef] 102. Genco, E.; Fattori, M.; Harpe, P.J.A.; Modena, F.; Viola, F.A.; Caironi, M.; Cantatore, E. A 4 × 4 Biosensor Array With a 42- µ W/Channel Mul-tiplexed Current Sensitive Front-End Featuring 137-dB DR and Zeptomolar Sensitivity. IEEE Open J. Solid-State Circuits Soc. 2022, 2, 193–207. [CrossRef] 103. Zeng, J.; Kuang, L.; Miscourides, N.; Georgiou, P. A 128 × 128 Current-Mode Ultra-High Frame Rate ISFET Array with In-Pixel Calibration for Real-Time Ion Imaging. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 359–372. [CrossRef] 104. Zeng, J.; Miscourides, N.; Georgiou, P. A 128 × 128 Current-Mode Ultra-High Frame Rate ISFET Array for Ion Imaging. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018; pp. 359–372. [CrossRef] 105. Cong, Y.; Xu, M.; Zhao, D.; Wu, D. A 3600 × 3600 large-scale ISFET sensor array for high-throughput pH sensing. In Proceedings of the 2017 IEEE 12th International Conference on ASIC (ASICON), Guiyang, China, 25–28 October 2017; pp. 957–960. [CrossRef] 106. Chan, W.P.; Premanode, B.; Toumazou, C. 64 pH-ISFET averaging array employing global negative current feedback. Electron. Lett. 2009, 45, 536–537. [CrossRef] 107. Eversmann, B.; Jenkner, M.; Hofmann, F.; Paulus, C.; Brederlow, R.; Holzapfl, B. A 128 128 CMOS Biosensor Array for Extra- cellular Recording of Neural Activity. IEEE J. Solid-State Circuits 2003, 38, 2306–2317. [CrossRef] 108. Bao, B.; Karnaushenko, D.D.; Schmidt, O.G.; Song, Y.; Karnaushenko, D. Active Matrix Flexible Sensory Systems: Materials, Design, Fabrication, and Integration. Adv. Intell. Syst. 2022, 4, 2100253. [CrossRef] 109. Fattori, M.; Cardarelli, S.; Fijn, J.; Harpe, P.; Charbonneau, M.; Locatelli, D.; Lombard, S.; Laugier, C.; Tournon, L.; Jacob, S.; et al. A printed proximity-sensing surface based on organic pyroelectric sensors and organic thin-film transistor electronics. Nat. Electron. 2022, 5, 289–299. [CrossRef] 110. Luo, Z.; Peng, B.; Zeng, J.; Yu, Z.; Zhao, Y.; Xie, J.; Lan, R.; Ma, Z.; Pan, L.; Cao, K.; et al. Sub-thermionic, ultra-high-gain organic transistors and circuits. Nat. Commun. 2021, 12, 1928. [CrossRef] [PubMed] 111. Lafaye, C.; Rovira, M.; Demuru, S.; Wang, S.; Kim, J.; Kunnel, B.P.; Besson, C.; Fernandez-Sanchez, C.; Serra-Graells, F.; Margarit-Taulé, J.M.; et al. Real-time smart multisensing wearable platform for monitoring sweat biomarkers during exercise. In Proceedings of the BioCAS 2022—IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Systems for a Better Future, Taipei, Taiwan, 13–15 October 2022; pp. 173–177. 112. Cisneros-Fernandez, J.; Guimera-Brunet, A.; Garcia-Cortadella, R.; Schafer, N.; Garrido, J.A.; Teres, L.; Serra-Graells, F. A 1024-Channel GFET 10-bit 5-kHz 36-µW Read-Out Integrated Circuit for Brain JLECoG. In Proceedings of the ICECS 2020—27th IEEE International Conference on Electronics, Circuits and Systems, Glasgow, UK, 23–25 November 2020; pp. 1–4. 113. Saini, D.; Saini, S.; Negi, S. Modelling and comparison of single gate and dual gate organic thin film transistor. In Proceedings of the 2016 International Conference on Emerging Trends in Communication Technologies, ETCT, Dehradun, India, 18–19 November 2017; pp. 1–5. 114. Brotherton, S.D. Introduction to thin film transistors: Physics and technology of TFTs. In Introduction to Thin Film Transistors: Physics and Technology of TFTs; Springer International Publishing: New York, NY, USA, 2013; Volume 9783319000, pp. 1–488. 115. Digilent. Digilent. Analog Discovery 2—Digilent Reference Manual. Available online: https://digilent.com/reference/test-and- measurement/analog-discovery-2/reference-manual (accessed on 14 June 2023). 116. Claramunt, S.; Palau, G.; Arnal, A.; Crespo-Yepes, A.; Porti, M.; Ogier, S. Exploitation of OTFTs variability for PUFs imple- mentation and impact of aging. Solid State Electron. 2023, 207, 108698. [CrossRef] 117. Wu, S.-J.; Wu, Y.-C.; Tsai, H.-H.; Liao, H.-H.; Juang, Y.-Z.; Lin, C.-H.; Shang-Jing, W.; Yung-Chen, W.; Hann-Huei, T.; Hsin-Hao, L.; et al. ISFET-based pH sensor composed of a high transconductance CMOS chip and a disposable touch panel film as the sensing layer. In Proceedings of the 2015 IEEE SENSORS, Busan, Republic of Korea, 1–4 November 2015; pp. 1–4. [CrossRef] Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.