Index of tesis/2011/hdl_10803_96232/

Chaves Romero, Ferney Alveiro
Study and modeling of multi-gate transistors in the context of CMOS technology scaling
2012
https://ddd.uab.cat/record/106205
[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]1=Chaves_Romero,_Ferney_Alveiro2022-11-08 17:28 30  
[ ]2=Study_and_modeling_of_multi-gate_transistors...2022-11-08 17:28 87  
[ ]3=20122022-11-08 17:28 5  
[ ]4=1062052022-11-08 17:28 34  
[IMG]fac1de1.gif2013-04-24 13:01 294K 
[IMG]fac1de1.ico2013-04-24 13:01 13K 
[TXT]fac1de1.info2013-04-24 13:01 721K 
[ ]fac1de1.pdf2013-04-24 13:01 3.0M 
[TXT]fac1de1.txt2013-04-24 13:01 191K 
[TXT]hdl_10803_96232.dirinfo2024-09-16 17:59 350  
[ ]hdl_10803_96232.du2024-09-16 17:59 31  
[TXT]hdl_10803_96232.dupdirs2024-09-16 17:59 0  
[TXT]hdl_10803_96232.dupfiles2024-09-16 17:59 0  
[TXT]hdl_10803_96232.errors2024-09-16 17:59 0  
[TXT]hdl_10803_96232.md52024-09-16 17:59 46  
[TXT]hdl_10803_96232.sha12024-09-16 17:59 54  
[TXT]hdl_10803_96232.sha2562024-09-16 17:59 78  
[TXT]hdl_10803_96232.stats2024-09-16 17:59 319