Web of Science: 1 citations, Scopus: 1 citations, Google Scholar: citations
On the hardware implementation of the arithmetic elements of the pairwise orthogonal transform
Santos, Lucana (Universidad de Las Palmas de Gran Canaria. Instituto Universitario de Microelectrónica Aplicada)
Blanes Garcia, Ian (Universitat Autònoma de Barcelona. Departament d'Enginyeria de la Informació i de les Comunicacions)
García, Aday (Universidad de Las Palmas de Gran Canaria. Instituto Universitario de Microelectrónica Aplicada)
Serra-Sagristà, Joan (Universitat Autònoma de Barcelona. Departament d'Enginyeria de la Informació i de les Comunicacions)
López, José (Universidad de Las Palmas de Gran Canaria. Instituto Universitario de Microelectrónica Aplicada)
Sarminto, Roberto (Universidad de Las Palmas de Gran Canaria. Instituto Universitario de Microelectrónica Aplicada)

Date: 2015
Abstract: The pairwise orthogonal transform (POT) is an attractive alternative to the Kahrunen-Loève transform for spectral decorrelation in on-board multispectral and hyperspectral image compression due to its reduced complexity. This work validates that the low complexity of the POT makes it feasible for a space-qualified field-programmable gate array (FPGA) implementation. A register transfer level description of the arithmetic elements of the POT is provided with the aim of achieving a low occupancy of resources and making it possible to synthesize the design on a space-qualified RTAX2000S and RTAX2000S-DSP. In order to accomplish these goals, the operations of the POT are fine-tuned such that their implementation footprint is minimized while providing equivalent coding performance. The most computationally demanding operations are solved by means of a lookup table. An additional contribution of this paper is a bit-exact description of the mathematical equations that are part of the transform, defined in such a way that they can be solved with integer arithmetic and implementations that can be easily cross-validated. Experimental results are presented, showing that it is feasible to implement the components of the POT on the mentioned FPGA.
Note: Número d'acord de subvenció MINECO/TIN2012-38102-C03-03
Note: Número d'acord de subvenció AGAUR/2014/SGR-691
Rights: Aquest document està subjecte a una llicència d'ús Creative Commons. Es permet la reproducció total o parcial, la distribució, la comunicació pública de l'obra i la creació d'obres derivades, fins i tot amb finalitats comercials, sempre i quan es reconegui l'autoria de l'obra original. Creative Commons
Language: Anglès
Document: article ; recerca ; publishedVersion
Published in: Journal of applied remote sensing, Vol. 9 no. 1 (May 2015) , 097496, ISSN 1931-3195

DOI: 10.1117/1.JRS.9.097496


13 p, 2.0 MB

The record appears in these collections:
Research literature > UAB research groups literature > Research Centres and Groups (scientific output) > Engineering > Group on Interactive Coding of Images (GICI)
Articles > Research articles
Articles > Published articles

 Record created 2015-12-09, last modified 2020-08-16



   Favorit i Compartir