Per citar aquest document: http://ddd.uab.cat/record/137410
Development of digital application specific printed electronics circuits : from specification to final prototypes
Llamas, Manuel (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Mashayekhi, Mohammad (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Alcalde, Ana (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Carrabina Bordoll, Jordi (Universitat Autònoma de Barcelona. Centre d'Accessibilitat i Intel·ligència Ambiental de Catalunya)
Pallarès, Jofre (Universitat Autònoma de Barcelona. Grup de Disseny de Circuits i Sistemes Integrats)
Vila, Francesc (Universitat Autònoma de Barcelona. Grup de Disseny de Circuits i Sistemes Integrats)
Conde, Adrià (Universitat Autònoma de Barcelona. Grup de Disseny de Circuits i Sistemes Integrats)
Terés Terés, Lluís (Universitat Autònoma de Barcelona. Grup de Disseny de Circuits i Sistemes Integrats)

Data: 2015
Resum: This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i. e. , PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.
Nota: Número d'acord de subvenció EC/FP7/287682
Nota: Número d'acord de subvenció MINECO/TEC2011-29800-C03
Drets: Tots els drets reservats.
Llengua: Anglès
Document: article ; recerca ; acceptedVersion
Matèria: Digital circuits ; Electronic design automation ; Hardware description languages ; Printed circuit layout ; Prototypes
Publicat a: Journal of Display Technology, Vol. 11, No. 8 (August 2015) , p. 652-657, ISSN 1551-319X

DOI: 10.1109/JDT.2015.2404974


Post-print
6 p, 794.2 KB

El registre apareix a les col·leccions:
Articles > Articles de recerca
Articles > Articles publicats

 Registre creat el 2015-09-04, darrera modificació el 2016-06-04



   Favorit i Compartir