Multilevel 3-D Device Simulation Approach Applied to Deeply Scaled Nanowire Field Effect Transistors
Seoane, Natalia (Universidade de Santiago de Compostela. Centro Singular de Investigación en Tecnoloxías Intelixentes)
Kalna, Karol (Swansea University)
Cartoixà Soler, Xavier (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)
Garcia-Loureiro, Antonio (Universidade de Santiago de Compostela. Centro Singular de Investigación en Tecnoloxías Intelixentes)

Date:	2022
Abstract:	Three silicon nanowire (SiNW) field effect transistors (FETs) with 15-, 12. 5- and 10. 6-nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental ID - VG characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in k-space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed ID - VG characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations.
Grants:	Ministerio de Ciencia e Innovación RYC-2017-23312 Agencia Estatal de Investigación PID2019-104834GB-I00 Agencia Estatal de Investigación RTI2018-097876-B-C21
Rights:	Aquest document està subjecte a una llicència d'ús Creative Commons. Es permet la reproducció total o parcial, la distribució, la comunicació pública de l'obra i la creació d'obres derivades, fins i tot amb finalitats comercials, sempre i quan es reconegui l'autoria de l'obra original.
Language:	Anglès
Document:	Article ; recerca ; Versió publicada
Subject:	Drift-diffusion (DD) ; Monte Carlo (MC) ; Nanowire (NW) ; Semiconductor device simulation ; Tight-binding (TB)
Published in:	IEEE Transactions on Electron Devices, Vol. 69, Issue 9 (September 2022) , p. 5276-5282, ISSN 0018-9383

DOI: 10.1109/TED.2022.3188945

7 p, 1.4 MB

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