A Multi-Self-Cascoded Voltage Reference with 2.73-ppm/V Line Sensitivity and 20.1-ppm/°C Temperature Coefficient at 0.45-V Supply
Gagliardi, Francesco (Università di Pisa)
Bruschi, Paolo (Università di Pisa)
Piotto, Massimo (Università di Pisa)
Dei, Michele (Università di Pisa)
Sakouhi, Soumaya (Università di Pisa)
International Midwest Symposium on Circuits and Systems (68th : 2025 : Lansing, Michigan)

Publicación:	[Piscataway] : Institute of Electrical and Electronics Engineers, 2025
Resumen:	Recent advancements in low-power and low-voltage integrated circuits have spurred significant research interest, particularly for applications with demanding supply conditions. This work presents a single-branch voltage reference achieving exceptional immunity to supply voltage variations. Leveraging a Δ V-based approach, the design utilizes transistors with different channel lengths to exploit geometry-dependent threshold voltage differences, enabling effective temperature compensation. Additionally, a multi-self-cascoded technique enhances immunity to supply voltage variations. Post-layout simulations of a 0. 18 μ m CMOS design, operating with supply voltage as low as 0. 45 V, demonstrate a line sensitivity of 2. 73 ppm/V and a temperature coefficient of 20. 1 ppm/°C, with power consumption below 200 pW. The proposed architecture is shown to be a robust solution for implementing precise, low-voltage and low-power voltage references.
Ayudas:	European Commission 101115182
Derechos:	Aquest document està subjecte a una llicència d'ús Creative Commons. Es permet la reproducció total o parcial, la distribució, la comunicació pública de l'obra i la creació d'obres derivades, fins i tot amb finalitats comercials, sempre i quan es reconegui l'autoria de l'obra original.
Lengua:	Anglès
Documento:	Capítol de llibre ; recerca ; Versió acceptada per publicar
Materia:	Voltage reference ; Low power ; Low voltage ; Energy harvesting ; Temperature coefficient ; Line sensitivity ; PSRR ; Selfcascoded ; Reverse short-channel effect ; Temperature sensors ; Semiconductor device modeling ; Integrated circuits ; Power demand ; Circuits and systems ; Threshold voltage ; Transistors
Publicado en:	2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS), 2025, p. 380-384, ISBN 979-8-3315-8934-9

DOI: 10.1109/MWSCAS53549.2025.11244514

Postprint 5 p, 1.5 MB

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