Web of Science: 1 citas, Scopus: 3 citas, Google Scholar: citas
GPU implementation of bitplane coding with parallel coefficient processing for high performance image compression
Enfedaque Montes, Pablo (Universitat Autònoma de Barcelona. Departament d'Enginyeria de la Informació i de les Comunicacions)
Aulí Llinàs, Francesc (Universitat Autònoma de Barcelona. Departament d'Enginyeria de la Informació i de les Comunicacions)
Moure López, Juan Carlos (Universitat Autònoma de Barcelona. Departament d'Arquitectura de Computadors i Sistemes Operatius)

Fecha: 2017
Resumen: The fast compression of images is a requisite in many applications like TV production, teleconferencing, or digital cinema. Many of the algorithms employed in current image compression standards are inherently sequential. High performance implementations of such algorithms often require specialized hardware like field integrated gate arrays. Graphics Processing Units (GPUs) do not commonly achieve high performance on these algorithms because they do not exhibit fine-grain parallelism. Our previous work introduced a new core algorithm for wavelet-based image coding systems. It is tailored for massive parallel architectures. It is called bitplane coding with parallel coefficient processing (BPC-PaCo). This paper introduces the first high performance, GPU-based implementation of BPC-PaCo. A detailed analysis of the algorithm aids its implementation in the GPU. The main insights behind the proposed codec are an efficient thread-to-data mapping, a smart memory management, and the use of efficient cooperation mechanisms to enable inter-thread communication. Experimental results indicate that the proposed implementation matches the requirements for high resolution (4 K) digital cinema in real time, yielding speedups of 30x with respect to the fastest implementations of current compression standards. Also, a power consumption evaluation shows that our implementation consumes 40 x less energy for equivalent performance than state-of-the-art methods.
Nota: Número d'acord de subvenció MINECO/472-02-2/2012
Nota: Número d'acord de subvenció MINECO/TIN2015-71126-R
Nota: Número d'acord de subvenció MINECO/TIN2014-53234-C2-1-R
Nota: Número d'acord de subvenció AGAUR/2014/SGR-691
Derechos: Tots els drets reservats
Lengua: Anglès.
Documento: article ; recerca ; acceptedVersion
Materia: Image coding ; SIMD computing ; Graphics processing unit (GPU) ; Compute unified device architecture (CUDA)
Publicado en: IEEE transactions on parallel and distributed systems, Vol. 28, issue 8 (Aug. 2017) , p. 2272-2284, ISSN 1045-9219

DOI: 10.1109/TPDS.2017.2657506

13 p, 1.2 MB

El registro aparece en las colecciones:
Documentos de investigación > Documentos de los grupos de investigación de la UAB > Centros y grupos de investigación (producción científica) > Ingeniería > Group on Interactive Coding of Images (GICI)
Artículos > Artículos de investigación
Artículos > Artículos publicados

 Registro creado el 2018-01-08, última modificación el 2019-02-02

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