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Pàgina inicial > Articles > Articles publicats > Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions |
Data: | 2021 |
Resum: | In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values. |
Ajuts: | Ministerio de Ciencia e Innovación PID2019-103869RB Ministerio de Ciencia e Innovación BES2017-080160 Ministerio de Economía y Competitividad TEC2016-75151-C3-R |
Drets: | Aquest document està subjecte a una llicència d'ús Creative Commons. Es permet la reproducció total o parcial, la distribució, i la comunicació pública de l'obra, sempre que no sigui amb finalitats comercials, i sempre que es reconegui l'autoria de l'obra original. No es permet la creació d'obres derivades. |
Llengua: | Anglès |
Document: | Article ; recerca ; Versió acceptada per publicar |
Matèria: | CMOS ; BTI ; HCI ; Parameters ; Extraction ; Method ; RTN ; Defects ; Aging |
Publicat a: | Solid-state electronics, Vol. 185 (November 2021) , art. 108037, ISSN 1879-2405 |
Postprint 5 p, 735.0 KB |