Power-efficient noise-induced reduction of reram cell's temporal variability effects
Ntinas, Vasileios (Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica)
Rubio, Antonio 1954- (Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica)
Sirakoulis, Georgios Ch (Democritus University of Thrace. Department of Electrical and Computer Engineering)
Salvador Aguilera, Emili (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)
Pedro, Marta (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)
Crespo Yepes, Albert (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)
Martin Martinez, Javier (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)
Rodríguez Martínez, Rosana (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)
Nafría i Maqueda, Montserrat (Universitat Autònoma de Barcelona. Departament d'Enginyeria Electrònica)

Data:	2021
Resum:	Resistive Random Access Memory (ReRAM) is a promising novel memory technology for non-volatile storing, with low-power operation and ultra-high area density. However, ReRAM memories still face issues through commercialization, mainly owing to the fact that the high fabrication variations and the stochastic switching of the manufactured ReRAM devices cause high Bit Error Rate (BER). Given that ReRAM devices are nonlinear elements, the nonlinear phenomenon of Stochastic Resonance (SR), which defines that an input disturbance with specific characteristics can improve the total performance of the nonlinear system, is used to reduce the ReRAM cell's BER. Thus, in this brief, the BER of a single ReRAM cell is explored, using the Stanford PKU model, and is improved after the application of specific additive input noise. The power dissipation of the proposed approach is also evaluated and compared with the consideration of higher amplitude writing pulses in the lack of noise, showing that the proposed noise-induced technique can decrease the BER without the excessive increase of the power dissipation. As a first step, towards the experimental verification of the proposed method, noise-induced measurements on a single fabricated ReRAM device are also performed. Overall, the presented results of the BER reduction with low power dissipation, reaching up to 3. 26× less power consumption considering 100 ns writing pulses, are encouraging for ReRAM designers, delivering a circuit-level solution against the device-level problem.
Ajuts:	Ministerio de Ciencia e Innovación PID2019-103869RB-C3
Drets:	Tots els drets reservats.
Llengua:	Anglès
Document:	Article ; recerca ; Versió acceptada per publicar
Matèria:	Emerging memories ; Memristor ; ReRAM devices ; Stochastic resonance ; Variability ; Electrical and Electronic Engineering
Publicat a:	IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 68, issue 4 (April 2021) , p. 1378-1382, ISSN 1558-3791

DOI: 10.1109/TCSII.2020.3026950

Postprint 6 p, 706.8 KB

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